Low voltage rail-to-rail CMOS output stage

• US 6,353,363 B1
• Filed: 02/29/2000
• Issued: 03/05/2002
• Est. Priority Date: 02/29/2000
• Status: Expired due to Term

• Current Assignee: SMSC Analog Technology Center, Inc. (Microchip Technology Incorporated), Seiko Instruments Incorporated (Seiko Group)
• Original Assignee: Gaia Technologies Incorporated (SAP SE), Seiko Instruments Incorporated (Seiko Group)
• Inventors: Stockstad, Troy L.
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Choe, Henry
• Application Number:
  US09/515,961
• Time in Patent Office: 735 Days
• Field of Search: 330/264, 330/267, 330/268
• US Class Current: 330/264
• CPC Class Codes: A61K 31/135 having aromatic rings , e.g. ketamine, nortriptyline methadone A61K31/137
• CPC Class Codes: A61K 31/15 Oximes (>C=N—O—); Hydrazines (>N—N<); Hydrazones (>N—N=) ; Imines (C—N=C)
• CPC Class Codes: A61K 31/34 having five-membered rings with one oxygen as the only ring hetero atom, e.g. isosorbide
• CPC Class Codes: A61K 31/445 Non condensed piperidines, e.g. piperocaine
• CPC Class Codes: H03F 3/3023 with asymmetrical driving of the end stage

Abstract

An output stage suitable for low voltage operation and capable of providing an essentially symmetrical rail-to-rail output voltage is disclosed. The output stage includes a first field effect device having a first drain, a first gate, and a first source coupled to a power supply V_CC. The output stage further includes a second field effect device complimentary to the first field effect device, having a second drain, a second gate, and a second source coupled to a power supply having a nominal voltage of V_EE. Further, the second drain is coupled to the first drain. Also included in the output stage is an output sink network coupled to the second field effect device. The output sink network drives the second field effect device such that a product of a current in the first field effect device and a current in the second field effect device is essentially equal to a predetermined constant during operation of the output stage.

Claims

1. An output stage suitable for low voltage operation and capable of providing a substantially symmetrical rail-to-rail output voltage, the output stage comprising:

a first field effect device having a first source, first drain, and first gate, the first source being coupled to a power supply V_CC;

a second field effect device complementary to the first field effect device, wherein the second field effect device includes a second source, second drain, and second gate, and wherein the second source is coupled to a power supply having a nominal voltage supply of V_EE and wherein the second drain is coupled to the first drain;

an output sink network coupled to the second gate, wherein the output sink network drives the second field effect device such that a product of a first current in the first field effect device and a second current in the second field effect device is essentially equal to a predetermined constant during operation of the out put stage; and

said first and second field effect devices and said output sink network producing a symmetrical rail-to-rail output voltage of no more than on V_GS and two V_DSAT from either rail.

2. An output stage as recited in claim 1, wherein a sum of the first current and the second current is essentially equal to a predetermined constant during operation of the output stage.

3. An output stage as recited in claim 1, wherein the first field effect device is configured in a common source configuration.

4. An output stage as recited in claim 1, wherein the first field effect device is a P-channel metal oxide semiconductor field effect (PMOS) transistor.

5. An output stage as recited in claim 4, wherein the second field effect device is an N-channel metal oxide semiconductor field effect (NMOS) transistor.

6. An output stage as recited in claim 5, wherein the output sink network utilizes a current mirror to track the current in the first field effect device.

7. An output stage as recited in claim 6, wherein the current mirror tracks the current in the first field effect device at a predetermined ratio of the current in the first field effect device.

8. An output stage as recited in claim 1, wherein the first field effect device is an N-channel metal oxide semiconductor field effect (NMOS) transistor.

9. An output stage as recited in claim 8, wherein the second field effect device is a P-channel metal oxide semiconductor field effect (PMOS) transistor.

10. A method for providing an output signal from an output stage of a low voltage operation amplifier capable of providing a substantially rail-to-rail output voltage, the method comprising the operations of:

providing an input signal to a first field effect device having a first source, first drain, and first gate, the first source being coupled to a power supply V_CC;

driving a second complementary field effect device utilizing an output sink network such that a product of a first current in the first field effect device and a second current in the second field effect device is essentially equal to a predetermined constant during operation of the amplifier; and

producing a symmetrical rail-to-rail output voltage, the rail-to-rail output voltage being no more than one V_GS and two V_DSAT from either rail.

11. A method as recited in claim 10, wherein a sum of the first current and the second current is essentially equal to a predetermined constant during operation of the amplifier.

12. A method as recited in claim 10, wherein the first field effect device is configured in a common source configuration.

13. A method as recited in claim 12, wherein the first field effect device is a P-channel metal oxide semiconductor field effect (PMOS) transistor.

14. A method as recited in claim 13, wherein the second field effect device is an N-channel metal oxide semiconductor field effect (NMOS) transistor.

15. A method as recited in claim 14, further comprising the operation of tracking the current in the first field effect device utilizing a current mirror.

16. A method as recited in claim 15, wherein the current mirror tracks the current in the first field effect device at a predetermined ratio.

17. An application specific integrated circuit (ASIC) having an output stage for a low voltage operational amplifier, the ASIC comprising:

a first field effect device having a first source, first drain, and first gate, the first source being coupled to a power supply V_CC;

a second field effect device complementary to the first field effect device, wherein the second field effect device includes a second source, second drain, and second gate, and wherein the second source is coupled to a power supply having a nominal voltage supply of V_EE and wherein the second drain is coupled to the first drain;

an output sink network coupled to the second gate, wherein the output sink network drives the second field effect device such that a product of a first current in the first field effect device and a second current in the second field effect device is essentially equal to a predetermined constant during operation of the output stage; and

said first and second field effect devices and said output sink network producing a symmetrical rail-to-rail output voltage of no more than one V_GS and two V_DSAT from either rail.

18. An ASIC as recited in claim 17, wherein the first field effect device is configured in a common source configuration.

19. An ASIC as recited in claim 17, wherein the first field effect device is a P-channel metal oxide semiconductor field effect (PMOS) transistor.

20. An ASIC as recited in claim 19, wherein the second field effect device is an N-channel metal oxide semiconductor field effect (NMOS) transistor.

21. An ASIC as recited in claim 20, wherein the output sink network utilizes a current mirror to track the current in the first field effect device.

22. An ASIC as recited in claim 21, wherein the current mirror tracks the current in the first field effect device at a predetermined ratio.

23. An ASIC as recited in claim 22, wherein the predetermined ratio is about 6:

1.