Cache organization—direct mapped cache

• US 6,353,438 B1
• Filed: 02/03/1999
• Issued: 03/05/2002
• Est. Priority Date: 02/03/1999
• Status: Expired due to Term

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ARTX
• Inventors: Van Hook, Timothy, DeLaurier, Anthony P.
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US09/244,690
• Time in Patent Office: 1,126 Days
• Field of Search: 345/552, 345/557, 345/540, 345/556, 345/430, 345/564, 345/419, 345/561, 345/428, 345/429, 345/582, 345/583, 345/587, 711/118, 711/127, 711/128, 711/154, 711/157
• US Class Current: 345/552
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06T 1/60 Memory management

Abstract

The invention provides for cache organization of texture information and a method and apparatus for accessing cached texture information and an index for cached information. Texels are represented in two dimensions and stored in groups referred to as tiles. Cache is configured to contain multiple tiles of texture image data, each tile being stored as a line in the cache. A cache line can be multidimensional (e.g., two or three or more dimensions) and may be viewed as an identifiable storage element in the cache. Memory may consist of a plurality of cache lines. Direct mapped cache may be utilized wherein each DRAM location maps to a single cache line. A tag table contains the tag information for all tiles currently stored in cache. A portion of the texel information may be utilized as an index assigned to a specific cache line. Another portion of the tag information identifies the tile currently stored in cache. A portion of the S bits and a portion of the T bits are utilized as the index and tile information. The tags may be organized into sections (referred to as tag banks) with the cache lines interleaved in two dimensions across the tag banks. Additionally, when mipmapping, the level of detail may be specified as part of the tag information. Cache access requests that are not currently active may also be stored in an interleaved list or queue until they are completed.

Claims

1. A method for accessing tag information in memory comprising:

obtaining an address of pixel texture image coordinates;

obtaining a first subset of s and t bits to indicate a tag index;

obtaining a second subset of s and t bits to indicate a tag bank; and

performing a plurality of accesses of said tag information in said memory using cache line texture image coordinates, said cache line texture image coordinates comprising said first subset and said second subset, wherein said cache line texture image coordinates are interleaved across said memory.

2. The method of claim 1 wherein said cache line texture image coordinates are interleaved across one or more banks.

3. The method of claim 1 wherein said cache line texture image coordinates are interleaved across one or more ports.

4. The method of claim 1 wherein said cache line texture image coordinates are two dimensional.

5. The method of claim 1 wherein said cache line texture image coordinates are three or more dimensional.

6. The method of claim 1 wherein said pixel texture image coordinates are two dimensional.

7. The method of claim 1 wherein said pixel texture image coordinates are three or more dimensional.

8. The method of claim 7 wherein one of said dimensions is a level of detail with mipmapped images.

9. The method of claim 7 wherein one of said dimensions is a image or array number.

10. A method for accessing information in cache memory, said cache memory comprising a plurality of storage elements uniquely identified by a tag, said method comprising:

obtaining an address of pixel texture image coordinates;

obtaining a first subset of s and t bits to indicate a tag index;

obtaining a second subset of s and t bits to indicate a tag bank; and

performing a plurality of accesses of said information in said cache memory using texel texture image coordinates, said textel texture image coordinates comprising said first subset and said second subset, wherein said texel texture image coordinates are interleaved across said cache memory.

11. The method of claim 10 wherein said texel texture image coordinates are interleaved across one or more banks.

12. The method of claim 10 wherein said texel texture image coordinates are interleaved across one or more ports.

13. The method of claim 10 wherein said texel texture image coordinates are two dimensional.

14. The method of claim 10 wherein said texel texture image coordinates are three or more dimensional.

15. The method of claim 10 wherein said pixel texture image coordinates are two dimensional.

16. The method of claim 10 wherein said pixel texture image coordinates are three or more dimensional.

17. The method of claim 16 wherein one of said dimensions is a level of detail with mipmapped images.

18. The method of claim 16 wherein one of said dimensions is a image or array number.

19. A method for accessing texel image information in memory, said method comprising:

obtaining pixel texture image coordinates;

obtaining a plurality of texel image coordinates by performing a neighborhood operation using said pixel texture image coordinates, each of said plurality of texel image coordinates uniquely identified by a tag;

performing a plurality of accesses of said texel image information in said memory using said texel image coordinates, wherein said texel image coordinates are comprised of a first subset of s and t bits to indicate a tag index and a second subset of s and t bits to indicate a tag bank.

20. The method of claim 19 wherein said memory is cache memory.

21. The method of claim 20 wherein said performing a plurality of accesses step is performed across a plurality of cache memory banks and said texel image information is interleaved across said cache memory banks.

22. The method of claim 19 wherein said memory is tag memory.

23. The method of claim 22 wherein said performing a plurality of accesses step is performed across a plurality of tag memory banks and said texel image information is interleaved across said tag memory banks.

24. The method of claim 19 wherein said neighborhood operation comprises an arithmetic operation.

25. The method of claim 19 wherein said neighborhood operation comprises a logical operation.

26. The method of claim 19 wherein said neighborhood operation comprises texture filter operation.

27. The method of claim 19 wherein said texel image coordinates are two dimensional.

28. The method of claim 19 wherein said texel image coordinates are three or more dimensional.

29. The method of claim 19 wherein said performing a plurality of accesses of said texel image information are performed in parallel.

30. The method of claim 19 wherein said performing a plurality of accesses of said texel image information are performed serially.

31. A method for processing pending cache access requests comprising obtaining a pending cache access request from memory based on texture image coordinates of a cache line, said texture image coordinates comprised of a first subset of s and t bits to indicate a tag index and a second subset of s and t bits to indicate a tag bank, said memory interleaved by said texture image coordinates of said cache line.

32. The method of claim 31 wherein said memory is interleaved across one or more banks.

33. The method of claim 31 wherein said memory is interleaved across one or more ports.

34. The method of claim 31 wherein said texture image coordinates are two dimensional.

35. The method of claim 31 wherein said texture image coordinates are three or more dimensional.

36. The method of claim 35 wherein one of said dimensions is a level of detail with mipmapped images.

37. The method of claim 35 wherein one of said dimensions is a image or array number.

38. A computer program product comprising:

a computer usable medium having computer readable program code embodied therein for accessing tag image information in memory, said computer program product comprising;

computer readable code configured to cause a computer to obtain an address of pixel texture image coordinates;

computer readable code configured to cause a computer to obtain a first subset of s and t bits to indicate a tag index;

computer readable code configured to cause a computer to obtain a second subset of s and t bits to indicate a tag bank; and

computer readable code configured to cause said computer to perform a plurality of accesses of said tag information in said memory using cache line texture image coordinates, said cache line texture image coordinates comprising said first subset and said second subset, wherein said cache line texture image coordinates are interleaved across said memory.

39. The computer program product of claim 38 wherein said cache line texture image coordinates are interleaved across one or more banks.

40. The computer program product of claim 38 wherein said cache line texture image coordinates are interleaved across one or more ports.

41. The computer program product of claim 38 wherein said cache line texture image coordinates are two dimensional.

42. The computer program product of claim 38 wherein said cache line texture image coordinates are three or more dimensional.

43. The computer program product of claim 38 wherein said pixel texture image coordinates are two dimensional.

44. The computer program product of claim 38 wherein said pixel texture image coordinates are three or more dimensional.

45. The computer program product of claim 44 wherein one of said dimensions is a level of detail with mipmapped images.

46. The computer program product of claim 44 wherein one of said dimensions is a image or array number.

47. A computer program product comprising:

a computer usable medium having computer readable program code embodied therein for accessing information in cache memory, said cache memory comprising a plurality of storage elements uniquely identified by a tag, said computer program product comprising;

computer readable code configured to cause a computer to obtain an address of pixel texture image coordinates;

computer readable code configured to cause a computer to obtain a first subset of s and t bits to indicate a tag index;

computer readable code configured to cause a computer to obtain a second subset of s and t bits to indicate a tag bank; and

computer readable code configured to cause a computer to perform a plurality of accesses of said information in said cache memory using texel texture image coordinates, said texel texture image coordinates comprising said first subset and said second subset, wherein said texel texture image coordinates are interleaved across said cache memory.

48. The computer program product of claim 47 wherein said texel texture image coordinates are interleaved across one or more banks.

49. The computer program product of claim 47 wherein said texel texture image coordinates are interleaved across one or more ports.

50. The computer program product of claim 47 wherein said texel texture image coordinates are two dimensional.

51. The computer program product of claim 47 wherein said texel texture image coordinates are three or more dimensional.

52. The computer program product of claim 47 wherein said pixel texture image coordinates are two dimensional.

53. The computer program product of claim 47 wherein said pixel texture image coordinates are three or more dimensional.

54. The computer program product of claim 53 wherein one of said dimensions is a level of detail with mipmapped images.

55. The computer program product of claim 53 wherein one of said dimensions is a image or array number.

56. A computer program product comprising:

a computer usable medium having computer readable program code embodied therein for accessing texel image information in memory, said computer program product comprising;

computer readable code configured to cause a computer to obtain pixel texture image coordinates;

computer readable code configured to cause a computer to obtain a plurality of texel image coordinates by performing a neighborhood operation using said pixel texture image coordinates, each of said plurality of texel image coordinates uniquely identified by a tag, said tag comprising a first subset of s and t bits to indicate a tag index and a second subset of s and t bits to indicate a tag bank; and

computer readable code configured to cause a computer to perform a plurality of accesses of said texel image information in said memory using said texel image coordinates.

57. The computer program product of claim 56 wherein said memory is cache memory.

58. The computer program product of claim 57 wherein said computer readable code configured to cause a computer to perform a plurality of accesses step is performed across a plurality of cache memory banks and said texel image information is interleaved across said cache memory banks.

59. The computer program product of claim 56 wherein said memory is tag memory.

60. The computer program product of claim 59 wherein said computer readable code configured to cause a computer to perform a plurality of accesses step is performed across a plurality of tag memory banks and said texel image information is interleaved across said tag memory banks.

61. The computer program product of claim 56 wherein said neighborhood operation comprises an arithmetic operation.

62. The computer program product of claim 56 wherein said neighborhood operation comprises a logical operation.

63. The computer program product of claim 56 wherein said neighborhood operation comprises texture filter operation.

64. The computer program product of claim 56 wherein said texel image coordinates are two dimensional.

65. The computer program product of claim 56 wherein said texel image coordinates are three or more dimensional.

66. The computer program product of claim 56 wherein said performing a plurality of accesses of said texel image information are performed in parallel.

67. The computer program product of claim 56 wherein said computer readable code configured to cause a computer to perform a plurality of accesses of said texel image information are performed serially.

68. A computer program product comprising a computer usable medium having a computer readable program code embodied therein for processing pending cache access requests, said computer program product comprising computer readable program code configured to cause a computer to obtain a pending cache access request from memory based on texture image coordinates of a cache line, said texture image coordinates comprising a first subset of s and t bits to indicate a tag index and a second subset of s and t bits to indicate a tag bank, said memory interleaved by said texture image coordinates of said cache line.

69. The computer program product of claim 68 wherein said memory is interleaved across one or more banks.

70. The computer program product of claim 68 wherein said memory is interleaved across one or more ports.

71. The computer program product of claim 68 wherein said texture image coordinates are two dimensional.

72. The computer program product of claim 68 wherein said texture image coordinates are three or more dimensional.

73. The computer program product of claim 72 wherein one of said dimensions is a level of detail with mipmapped images.

74. The computer program product of claim 72 wherein one of said dimensions is a image or array number.

75. A system comprising

a processor;

a memory coupled to said processor;

code executed by said processor for accessing tag information in memory;

said code comprising;

a method obtaining an address of pixel texture image coordinates;

a method of obtaining a first subset of s and t bits to indicate a tag index;

a method of obtaining a second subset of s and t bits to indicate a tag bank; and

a method performing a plurality of accesses of said tag information in said memory using cache line texture image coordinates, said cache line texture image coordinates comprising said first subset and said second subset, wherein said cache line texture image coordinates are interleaved across said memory.

76. The system of claim 75 wherein said cache line texture image coordinates are interleaved across one or more banks.

77. The system of claim 75 wherein said cache line texture image coordinates are interleaved across one or more ports.

78. The system of claim 75 wherein said cache line texture image coordinates are two dimensional.

79. The system of claim 75 wherein said cache line texture image coordinates are three or more dimensional.

80. The system of claim 75 wherein said pixel texture image coordinates are two dimensional.

81. The system of claim 75 wherein said pixel texture image coordinates are three or more dimensional.

82. The system of claim 81 wherein one of said dimensions is a level of detail with mipmapped images.

83. The system of claim 81 wherein one of said dimensions is a image or array number.

84. A system comprising

a processor;

a memory coupled to said processor;

code executed by said processor for accessing information in cache memory, said cache memory comprising a plurality of storage elements uniquely identified by a tag;

said code comprising;

a method obtaining an address of pixel texture image coordinates;

a method of obtaining a first subset of s and t bits to indicate a tag index;

a method of obtaining a second subset of s and t bits to indicate a tag bank; and

a method performing a plurality of accesses of said information in said cache memory using texel texture image coordinates, said texel texture image coordinates comprising said first subset and said second subset, wherein said textel texture image coordinates are interleaved across said cache memory.

85. The system of claim 84 wherein said texel texture image coordinates are interleaved across one or more banks.

86. The system of claim 84 wherein said texel texture image coordinates are interleaved across one or more ports.

87. The system of claim 84 wherein said texel texture image coordinates are two dimensional.

88. The system of claim 84 wherein said texel texture image coordinates are three or more dimensional.

89. The system of claim 84 wherein said pixel texture image coordinates are two dimensional.

90. The system of claim 84 wherein said pixel texture image coordinates are three or more dimensional.

91. The system of claim 90 wherein one of said dimensions is a level of detail with mipmapped images.

92. The system of claim 90 wherein one of said dimensions is a image or array number.

93. A system comprising

a processor;

a memory coupled to said processor;

code executed by said processor for accessing texel image information in memory;

said code comprising;

a method obtaining pixel texture image coordinates;

a method obtaining a plurality of texel image coordinates by performing a neighborhood operation using said pixel texture image coordinates, each of said plurality of texel image coordinates uniquely identified by a tag, said tag comprising a first subset of s and t bits to indicate a tag index and a second subset of s and t bits to indicate a tag bank; and

a method performing a plurality of accesses of said texel image information in said memory using said texel image coordinates.

94. The system of claim 93 wherein said memory is cache memory.

95. The system of claim 94 wherein said method performing a plurality of accesses is performed across a plurality of cache memory banks and said texel image information is interleaved across said cache memory banks.

96. The system of claim 93 wherein said memory is tag memory.

97. The system of claim 96 wherein said method performing a plurality of accesses is performed across a plurality of tag memory banks and said texel image information is interleaved across said tag memory banks.

98. The system of claim 93 wherein said neighborhood operation comprises an arithmetic operation.

99. The system of claim 93 wherein said neighborhood operation comprises a logical operation.

100. The system of claim 93 wherein said neighborhood operation comprises texture filter operation.

101. The system of claim 93 wherein said texel image coordinates are two dimensional.

102. The system of claim 93 wherein said texel image coordinates are three or more dimensional.

103. The system of claim 93 wherein said performing a plurality of accesses of said texel image information are performed in parallel.

104. The system of claim 93 wherein said performing a plurality of accesses of said texel image information are performed serially.

105. A system comprising

a processor;

a memory coupled to said processor;

code executed by said processor for processing pending cache access requests;

said code comprising;

a method obtaining a pending cache access request from memory based on texture image coordinates of a cache line, said texture image coordinates comprising a first subset of s and t bits to indicate a tag index and a second subset of s and t bits to indicate a tag bank, said memory interleaved by said texture image coordinates of said cache line.

106. The system of claim 105 wherein said memory is interleaved across one or more banks.

107. The system of claim 105 wherein said memory is interleaved across one or more ports.

108. The system of claim 105 wherein said texture image coordinates are two dimensional.

109. The system of claim 105 wherein said texture image coordinates are three or more dimensional.

110. The system of claim 109 wherein one of said dimensions is a level of detail with mipmapped images.

111. The system of claim 109 wherein one of said dimensions is a image or array number.