Television receiver, video signal processing device, image processing device and image processing method

• US 6,353,460 B1
• Filed: 09/29/1998
• Issued: 03/05/2002
• Est. Priority Date: 09/30/1997
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation), Texas Instruments, Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation), Texas Instruments, Inc.
• Inventors: Tani, Masahiro, Miyaguchi, Hiroshi, Tokunaga, Naoya, Miki, Yoichiro, Sokawa, Kenta, Ninomiya, Kazuki, Yaguchi, Yuji, Akiyama, Tsuyoshi
• Primary Examiner(s): Lee, Michael
• Assistant Examiner(s): Yenke, Brian P.
• Application Number:
  US09/162,740
• Time in Patent Office: 1,253 Days
• Field of Search: H04/N.327, H04/N.546, H04/N.5268, 348/554, 348/555, 348/556, 348/557, 348/558, 348/706
• US Class Current: 348/555
• CPC Class Codes: H04N 21/4316 for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/440218 by transcoding between formats or standards, e.g. from MPEG-2 to MPEG-4 conversion of standards in analogue television systems H04N7/01
• CPC Class Codes: H04N 21/4622 Retrieving content or additional data from different sources, e.g. from a broadcast channel and the Internet web site content organization and management for information retrieval from the Internet G06F16/958; transmission by internet of broadcast information H04H60/82; stock exchange data over packet-switching network H04L12/1804; push services including data channel over packet-switching network H04L12/1859
• CPC Class Codes: H04N 5/45 Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 5/46 for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 5/907 using static stores, e.g. storage tubes or semiconductor memories H04N5/91 takes precedence
• CPC Class Codes: H04N 7/01 Conversion of standards , e.g. involving analogue television standards or digital television standards processed at pixel level
• CPC Class Codes: H04N 7/0122 the input and the output signals having different aspect ratios

Abstract

The television receiver including a display device capable of displaying a video signal having a predetermined display former of this invention includes; a plurality of video signal sources; a selection circuit for selecting one of a plurality of video signals output from the plurality of video signal sources; and an image processor for converting a format of the video signal selected by the selection circuit into the predetermined display format, wherein a video signal output from the processor is supplied to the display device.

Claims

1. An image processing device comprising:

an input section for receiving image data to be processed;

a digital signal processing section including (a) a data input portion for receiving in parallel for each scanning line at least one image data unit corresponding to at least one respective video signal;

(b) a plurality of processing elements allocated to respective pixels corresponding to one scanning line in a one-to-one relationship for performing a same operation in accordance with a common instruction, and (c) a data output portion for outputting in parallel for each scanning line the at least one image data unit processed for each scanning line by the plurality of processing elements, the digital signal receiving, processing and outputting the image data for each scanning line,

an image memory having a fixed memory region and capable of performing a write operation and a read operation in parallel and independently, the image memory receiving and outputting the image data for each scanning line;

an output section for outputting processed image data;

data but means for connecting the input section, the digital signal processing section, the image memory, and the output section with one another; and

control means for controlling the input section, the digital signal processing section, the image memory, and the output section in accordance with program data,

wherein a data input operation for each scanning line by the data input portion, a processing operation for each scanning line by the plurality of processing elements, and a data output operation for each scanning line by the data output section are performed in a pipeline manner.

2. An image processing device comprising:

an input section for receiving image data to be processed;

a digital signal processing section including a plurality of processing elements allocated to respective pixels corresponding to one scanning line in a one-to-one relationship for performing a same operation in accordance with a common instruction, the digital signal receiving, processing and outputting the image data for each scanning line;

an image memory having a fixed memory region and capable of performing a write operation and a read operation in parallel and independently, the image memory receiving and outputting the image data for each scanning line and including data write means for sequentially writing the input image data into the memory region in sequential addresses;

data read means for reading the image data to be output from the memory region in sequential addresses; and

pointer control means for controlling a write pointer and a read pointer for indicating a write address and a read address in the memory region, respectively, in accordance with program data;

an output section for outputting processed image data;

data bus means for connecting the input section, the digital signal processing section, the image memory, and the output section with one another; and

control means for controlling the input section, the digital signal processing section, the image memory, and the output section in accordance with program data.

3. An image processing device according to claim 2, wherein the image memory further includes:

a plurality of input buffers each having at least first and second input buffer portions with a respective predetermined memory capacity; and

means for controlling the plurality of input buffers such that when the first input buffer portion of the input buffer is filled with image data, writing of input image data into the second input buffer portion is started, and image data is read from the first input buffer portion to be written into the memory region, and

when the second input buffer portion is filled with image data, writing of input image data into the first input buffer portion is started, and image data is read from the second input buffer portion to be written into the memory region.

4. An image processing device according to claim 3, wherein a data rate at which image data is written into the memory region from the input buffer is selected to be different from a data rate at which image data is written into the input buffer.

5. An image processing device according to claim 2, wherein the image memory further includes:

a plurality of output buffers each having at least first and second output buffer portions with a respective predetermined memory capacity; and

means for controlling the plurality of output buffers such that when the first output buffer portion of the output buffer has no image data, reading of image data from the second output buffer portion is started, and image data read from the memory region is written into the first output buffer portion, and

when the second output buffer portion has no image data, reading of image data from the first output buffer portion is started, and image data read from the memory region is written into the second output buffer portion.

6. An image processing device according to claim 5, wherein a data rate at which image data is written into the output buffer from the memory region is selected to be different from a data rate at which image data is read from the output buffer.

7. An image processing device comprising:

an input section for receiving image data to be processed;

a digital signal processing section including a plurality of processing elements allocated to respective pixels corresponding to one scanning line in a one-to-one relationship for performing a same operation in accordance with a common instruction, the digital signal receiving, processing and outputting the image data for each scanning line;

an image memory having a fixed memory region and capable of performing a write operation and a read operation in parallel and independently, the image memory receiving and outputting the image data for each scanning line;

an output section for outputting processed image data;

data bus means for connecting the input section, the digital signal processing section, the image memory, and the output section with one another and including a first data bus portion for electrically connecting a data output terminal of the input section with a data input terminal of the digital signal processing section;

a second data bus portion for electrically connecting a data output terminal of the input section with a data input terminal of the image memory;

a third data bus portion for electrically connecting a data output terminal of the digital signal processing section with a data input terminal of the image memory;

a fourth data bus portion for electrically connecting a data output terminal of the image memory with a data input terminal of the digital signal processing section;

a fifth data bus portion for electrically connecting a data output terminal of the input section with a data input terminal of the output section;

a sixth data bus portion for electrically connecting a data output terminal of the digital signal processing section with a data input terminal of the output section; and

a seventh data bus portion for electrically connecting a data output terminal of the image memory with a data input terminal of the output section; and

control means for controlling the input section, the digital signal processing section, the image memory, and the output section in accordance with program data.

8. An image processing device according to claim 7, wherein all of the first to seventh data bus portions are formed on a semiconductor chip.

9. An image processing device comprising:

an input section for receiving image data to be processed;

a digital signal processing section including a plurality of processing elements allocated to respective pixels corresponding to one scanning line in a one-to-one relationship for performing a same operation in accordance with a common instruction, the digital signal receiving, processing and outputting the image data for each scanning line;

an image memory having a fixed memory region and capable of performing a write operation and a read operation in parallel and independently, the image memory receiving and outputting the image data for each scanning line;

an output section for outputting processed image data;

data bus means for connecting the input section, the digital signal processing section, the image memory, and the output section with one another; and

control means for controlling the input section, the digital signal processing section, the image memory, and the output section in accordance with program data and including program data holding means for holding program data defining operation modes for the input section, the digital signal processing section, the image memory, the output section, and the data bus means; and

program data distribution means for receiving program data and distributing the program data into the program data holding means.

10. An image processing method for processing image data by an image processing device comprising:

an input section for receiving image data to be processed;

a digital signal processing section including a plurality of processing elements allocated to respective pixels corresponding to one scanning line in a one-to-one relationship for performing a same operation in accordance with a common instruction, the digital signal receiving, processing and outputting the image data for each scanning line;

an image memory having a fixed memory region and capable of performing a write operation and a read operation in parallel and independently, the image memory receiving and outputting the image data for each scanning line;

an output section for outputting processed image data;

data bus means for connecting the input section, the digital signal processing section, the image memory, and the output section with one another; and

control means for controlling the input section, the digital signal processing section, the image memory, and the output section in accordance with program data,

the method comprising the steps of;

receiving image data corresponding to one video signal by the input section;

performing a first processing for the image data output from the input section to the digital signal processing section by the digital signal processing section;

writing the image data output from the digital signal processing section after the first processing into the image memory to temporarily store the image data in the image memory; and

receiving the image data read from the image memory by the digital signal processing section again to perform a second processing.

11. An image processing method according to claim 10, further comprising the steps of:

writing the image data output from the digital signal processing section after the second processing into the image memory to temporarily store the image data in the image memory; and

receiving the image data read from the image memory by the digital signal processing section again to perform a third processing.

13. An image processing method according to claim 11, wherein the image data is read from two output ports of the image memory by delaying the image data by a predetermined delay amount and input in parallel into the digital signal processing section, and the predetermined processing is performed between the two units of image data from the image memory and the image data from the input section.

12. An image processing method for processing image data by an image processing device comprising:

an input section for receiving image data to be processed;

a digital signal processing section including a plurality of processing elements allocated to respective pixels corresponding to one scanning line in a one-to-one relationship for performing a same operation in accordance with a common instruction, the digital signal receiving, processing and outputting the image data for each scanning line;

an image memory having a fixed memory region and capable of performing a write operation and a read operation in parallel and independently, the image memory receiving and outputting the image data for each scanning line;

an output section for outputting processed image data;

data bus means for connecting the input section, the digital signal processing section, the image memory, and the output section with one another; and

control means for controlling the input section, the digital signal processing section, the image memory, and the output section in accordance with program data,

the method comprising the steps of;

receiving image data corresponding to one video signal by the input section;

writing the image data output from the input section into the image memory to temporarily store the image data in the image memory;

supplying the image data from the input section and the image data read from the image memory to the digital signal processing section in parallel, and performing a predetermined processing between these image data.

14. An image processing method for processing image data by an image processing device comprising:

an input section for receiving image data to be processed;

a digital signal processing section including a plurality of processing elements allocated to respective pixels corresponding to one scanning line in a one-to-one relationship for performing a same operation in accordance with a common instruction, the digital signal receiving, processing and outputting the image data for each scanning line;

an image memory having a fixed memory region and capable of performing a write operation and a read operation in parallel and independently, the image memory receiving and outputting the image data for each scanning line;

an output section for outputting processed image data;

data bus means for connecting the input section, the digital signal processing section, the image memory, and the output section with one another; and

control means for controlling the input section, the digital signal processing section, the image memory, and the output section in accordance with program data,

the method comprising the steps of;

writing only a portion of the image data corresponding to a portion of pixels for each scanning line and/or a portion of scanning lines for each field among the image data corresponding to one video signal into the image memory to temporarily store the portion of the image data in the image memory; and

reading from the image memory the image data in order in which the pixels and scanning lines have been written to the image memory.

15. An image processing method for processing image data by an image processing device comprising:

an input section for receiving image data to be processed;

a digital signal processing section including a plurality of processing elements allocated to respective pixels corresponding to one scanning line in a one-to-one relationship for performing a same operation in accordance with a common instruction, the digital signal receiving, processing and outputting the image data for each scanning line;

an image memory having a fixed memory region and capable of performing a write operation and a read operation in parallel and independently, the image memory receiving and outputting the image data for each scanning line;

an output section for outputting processed image data;

data bus means for connecting the input section, the digital signal processing section, the image memory, and the output section with one another; and

control means for controlling the input section, the digital signal processing section, the image memory, and the output section in accordance with program data,

the method comprising the steps of;

writing image data corresponding to one video signal into the image memory to temporarily store the image data in the image memory;

reading the image data from the image memory intermittently for each pixel or for each scanning line; and

supplying the image data read from the image memory to the digital signal processing section, and interpolating image data at positions of pixels or scanning lines which had been skipped in the intermittent reading of the image memory.

16. An image processing method for processing image data by an image processing device comprising:

an input section for receiving image data to be processed;

a digital signal processing section including a plurality of processing elements allocated to respective pixels corresponding to one scanning line in a one-to-one relationship for performing a same operation in accordance with a common instruction, the digital signal receiving, processing and outputting the image data for each scanning line;

an image memory having a fixed memory region and capable of performing a write operation and a read operation in parallel and independently, the image memory receiving and outputting the image data for each scanning line;

an output section for outputting processed image data;

data bus means for connecting the input section, the digital signal processing section, the image memory, and the output section with one another; and

control means for controlling the input section, the digital signal processing section, the image memory, and the output section in accordance with program data,

the method comprising the steps of;

receiving first and second image data units corresponding to two image signals which are asynchronous from each other by the input section;

writing the first image data unit output from the input section into the image memory to temporarily store the first image data in the image memory;

supplying the second image data unit output from the input section to the digital signal processing section, and simultaneously reading the first image data unit from the image memory to supply to the digital signal processing section in synchronization with the supply of the second image data unit; and

performing a predetermined processing for the first and second image data units input in synchronization with each other by the digital signal processing section.

17. An image processing method for processing image data by an image processing device comprising:

an input section for receiving image data to be processed;

a digital signal processing section including a plurality of processing elements allocated to respective pixels corresponding to one scanning line in a one-to-one relationship for performing a same operation in accordance with a common instruction, the digital signal receiving, processing and outputting the image data for each scanning line;

an image memory having a fixed memory region and capable of performing a write operation and a read operation in parallel and independently, the image memory receiving and outputting the image data for each scanning line;

an output section for outputting processed image data;

data bus means for connecting the input section, the digital signal processing section, the image memory, and the output section with one another; and

control means for controlling the input section, the digital signal processing section, the image memory, and the output section in accordance with program data,

the method comprising the steps of;

receiving first and second image data units corresponding to two image signals which are asynchronous from each other by the input section;

supplying the first image data unit output from the input section to the digital signal processing section to perform a predetermined processing;

supplying the first image data unit output from the digital signal processing section to the image memory, and simultaneously supplying the second image data unit output from the input section to the image memory; and

reading the first and second image data units from the image memory in synchronization with a synchronous signal other than synchronous signals relating to the first and second image data units.

18. An image processing method for processing image data by an image processing device comprising:

an input section for receiving image data to be processed;

a digital signal processing section including a plurality of processing elements allocated to respective pixels corresponding to one scanning line in a one-to-one relationship for performing a same operation in accordance with a common instruction, the digital signal receiving, processing and outputting the image data for each scanning line;

an image memory having a fixed memory region and capable of performing a write operation and a read operation in parallel and independently, the image memory receiving and outputting the image data for each scanning line;

an output section for outputting processed image data;

data bus means for connecting the input section, the digital signal processing section, the image memory, and the output section with one another; and

control means for controlling the input section, the digital signal processing section, the image memory, and the output section in accordance with program data,

the method comprising the steps of;

receiving image data corresponding to one video signal by the input section;

supplying a former half of the image data output from the input section to the digital signal processing section during a first period;

writing the image data output from the input section into the image memory and reading the written image data after a predetermined delay time; and

supplying a latter half of the image data output from the image memory to the digital signal processing section during a second period.

19. An image processing method according to claim 18, further comprising the steps of:

writing the former half of the image data output from the digital signal processing section into the image memory and reading the written image data after a predetermined delay time;

outputting the former half of the image data read from the image memory from the output section;

outputting the latter half of the image data from the digital signal processing section; and

outputting the latter half of the image data output from the digital signal processing section from the output section in succession with the former half of the image data.

20. An image processing method according to claim 19, further comprising the steps of:

adding a first overlap portion which overlaps a head portion of the latter half of the image data by a predetermined number of pixels to a tail portion of the former half of the image data input into the digital signal processing section during the first period;

adding a second overlap portion which overlaps a tail portion of the former half of the image data by a predetermined number of pixels to a head portion of the latter half of the image data input into the digital signal processing section during the second period; and

removing the first and second overlap portions at a stage of outputting the image data outside from the output section.

21. An image processing method for processing image data by an image processing device comprising:

an input section for receiving image data to be processed;

a digital signal processing section including a plurality of processing elements allocated to respective pixels corresponding to one scanning line in a one-to-one relationship for performing a same operation in accordance with a common instruction, the digital signal receiving, processing and outputting the image data for each scanning line;

an image memory having a fixed memory region and capable of performing a write operation and a read operation in parallel and independently, the image memory receiving and outputting the image data for each scanning line;

an output section for outputting processed image data;

data bus means for connecting the input section, the digital signal processing section, the image memory, and the output section with one another; and

control means for controlling the input section, the digital signal processing section, the image memory, and the output section in accordance with program data,

the method comprising the steps of;

receiving image data corresponding to one video signal by the input section and performing a low-pass filtering processing by the input section; and

supplying the image data output from the input section to the digital signal processing section or the image memory, and performing a decimation processing for information compression of the image data.

22. A video signal processing device comprising:

a first converter for receiving a plurality of video data units corresponding to a plurality of pixels connected to one scanning line as an input video signal, and converting the plurality of video data units into a plurality of video data sets, each of the plurality of video data sets including at least two video data units;

an operator for processing the plurality of video data sets and outputting a plurality of processed video data sets; and

a second converter for converting the plurality of processed video data sets into a plurality of processed video data units corresponding to a plurality of pixels connected to one scanning line, and outputting the plurality of processed video data units as an output video signal.

23. A video signal processing device according to claim 22, wherein the operator includes a plurality of processor elements, and each of the plurality of processor elements processes at least two image data units included in each of the plurality of video data sets.