TFT array substrate, liquid crystal display using TFT array substrate, and manufacturing method thereof in which the interlayer insulating film covers the guard resistance and the short ring

• US 6,353,464 B1
• Filed: 11/09/1999
• Issued: 03/05/2002
• Est. Priority Date: 11/20/1998
• Status: Expired due to Term

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Kabushiki Kaisha Advanced Display
• Inventors: Noumi, Shigeaki, Yabushita, Kouji
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): QI, ZHI QIANG
• Application Number:
  US09/437,090
• Time in Patent Office: 847 Days
• Field of Search: 349/42, 349/43, 349/48, 438/30, 438/180, 438/365
• US Class Current: 349/42
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer

Abstract

A manufacturing method of a liquid crystal display is provided. The liquid crystal display having a picture element electrode formed on the uppermost layer of a structure is capable of reducing connection resistance between picture element electrode and drain electrode through interlayer insulating film. At the time of forming the picture element electrode, ITO film can be patterned into a desirable pattern without short circuit between assembled terminals in one etching process. In the process of forming a contact hole 112 for connecting the picture element electrode 113 and the drain electrode 108 on the interlayer insulating film 111 and on the passivation film 110, a dry etching condition is established so that after the ashing process using O₂ gas to remove residue on the bottom of the contact hole 112, an etching process using fluorine gas +O₂ gas etc. is performed to reduce irregularity on the surface of the interlayer insulating film 111.

Claims

1. A TFT array substrate comprising:

a plurality of gate lines provided with a gate electrode and formed on a transparent insulating substrate;

a plurality of source lines provided with a source electrode and crossing over said gate lines;

a semiconductor layer provided on said gate electrode through a gate insulating film;

a thin film transistor comprised of said source electrode and said drain electrode connected to said semiconductor layer;

an interlayer insulating film formed on said substrate, and of which surface is flattened so as not to produce any step due to said thin film transistor;

a picture element electrode composed of a transparent conductive film provided in a wide spread manner on said interlayer insulating film and connected to said drain electrode through a contact hole formed on said interlayer insulating film; and

a terminal region in which terminals electrically connected to each of said gate lines and said source lines are arranged on the periphery of an image display section of said substrate to connect each terminal to an external terminal;

wherein said interlayer insulating film is provided on said image display section and on a peripheral edge portion, which includes at least an opposite end of said image display section side of each terminal in said terminal region and a guard resistance and a short ring respectively connected to said end, and

wherein said interlayer insulating film covers the guard resistance and the short ring.

4. The TFT array substrate according to any of claim 1, wherein an insulating film which is thick and of which section is not tapered is provided on a lower layer of each terminal in the terminal region so that width of the insulating film is larger than that of the terminals.

5. The TFT array substrate according to claim 1, wherein the interlayer insulating film is provided on the entire surface of the terminal region.

6. The TFT array substrate according to claim 1, wherein the interlayer insulating film is composed of a photosensitive resin.

7. A liquid crystal display comprising a liquid crystal arranged between the TFT array substrate according to claim 1 and an opposite electrode substrate having a transparent electrode, a color filter, etc.

2. A TFT array substrate, comprising:

a plurality of gate lines provided with a gate electrode and formed on a transparent insulating substrate;

a plurality of source lines provided with a source electrode and crossing over said gate lines;

a semiconductor layer provided on said gate electrode through a gate insulating film;

a thin film transistor comprised of said source electrode and said drain electrode connected to said semiconductor layer;

an interlayer insulating film formed on said substrate, and of which surface is flattened so as not to produce any step due to said thin film transistor;

a picture element electrode composed of a transparent conductive film provided in a wide spread manner on said interlayer insulating film and connected to said drain electrode through a contact hole formed on said interlayer insulating film; and

a terminal region in which terminals electrically connected to each of said gate lines and said source lines are arranged on the periphery of an image display section of said substrate to connect each terminal to an external terminal;

wherein said interlayer insulating film is provided not only on said image display section but also on a peripheral edge portion including at least an opposite end of said image display section side of each terminal in said terminal region and a guard resistance and a short ring respectively connected to said end,

wherein the interlayer insulating film is provided between respective terminals in the terminal region, and wherein a width of the interlayer insulating film is smaller than a distance between said respective terminals, said width and said distance being along a common direction.

3. A TFT array substrate, comprising:

a plurality of gate lines provided with a gate electrode and formed on a transparent insulating substrate;

a plurality of source lines provided with a source electrode and crossing over said gate lines;

a semiconductor layer provided on said gate electrode through a gate insulating film;

a thin film transistor comprised of said source electrode and said drain electrode connected to said semiconductor layer;

an interlayer insulating film formed on said substrate, and of which surface is flattened so as not to produce any step due to said thin film transistor;

a picture element electrode composed of a transparent conductive film provided in a wide spread manner on said interlayer insulating film and connected to said drain electrode through a contact hole formed on said interlayer insulating film;

a terminal region in which terminals electrically connected to each of said gate lines and said source lines are arranged on the periphery of an image display section of said substrate to connect each terminal to an external terminal; and

an insulating film provided between respective terminals in the terminal region, and wherein a width of the insulating film is smaller than a distance between said respective terminals, said width and said distance being along a common direction, said insulating film having a sectioned portion along the common direction wherein a profile of said sectioned portion is not tapered;

wherein said interlayer insulating film is provided not only on said image display section but also on a peripheral edge portion including at least an opposite end of said image display section side of each terminal in said terminal region and a guard resistance and a short ring respectively connected to said end.