Shared 5 volt tolerant ESD protection circuit for low voltage CMOS process

• US 6,353,520 B1
• Filed: 06/03/1999
• Issued: 03/05/2002
• Est. Priority Date: 06/03/1999
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Cline, Roger A., Andresen, Bernhard H.
• Primary Examiner(s): Leja, Ronald W.
• Application Number:
  US09/325,455
• Time in Patent Office: 1,006 Days
• Field of Search: 257/133, 257/173, 257/362, 257/357, 361/56, 361/91, 361/111, 361/212
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0251 for MOS devices

Abstract

An integrated circuit is provided with a local electrostatic discharge (ESD) protection circuitry (120) associated with each signal pad. The integrated circuit has internal circuitry (100) that operates at a low supply voltage, but at least some of the interface signals impressed on the signal pads operate at a high supply voltage. The local ESD protection circuitry associated with each signal pad comprises only a pair of diodes connected respectively to the ground reference bus and a high voltage supply bus. A few shared clamp circuits (222) are connected to the voltage buses and clamp any ESD voltage surge that is transferred to the high voltage bus by the individual signal pad ESD protection circuits. The clamp circuits use cascoded low voltage MOS devices (P1, N1, P2) that are biased during normal operation so that electrical over-stress does not occur.

Claims

1. An integrated circuit, comprising:

a semiconductor substrate connected to a bond pad for a reference supply voltage;

a first bus for a first supply voltage, and a second bus for a second supply voltage, wherein the second supply voltage is higher than the first supply voltage;

internal circuitry connected between the first bus and semiconductor substrate comprising MOS transistors having gate oxide with a first thickness suitable for the first supply voltage but not for the second supply voltage;

a plurality of signal bond pads for connecting to a respective plurality of external signals, wherein the plurality of external signals are operable at approximately the second supply voltage, with local ESD protection circuitry having a respective diode connected between each of the plurality of signal bond pads and the second bus; and

shared ESD circuitry connected between the second bus and the semiconductor substrate, wherein the shared ESD circuitry comprises;

at least one parasitic bipolar transistor with an emitter connected to the second bus and a collector connected to the semiconductor substrate with a base connected to a control circuit, wherein the control circuit comprises a plurality of MOS transistors each having gate oxide only of the first thickness such that the control circuit is operable to turn on the parasitic bipolar transistor in response to an ESD zap applied to any of the plurality of signal bond pads; and

wherein the control circuit further comprises an R/C timing circuit responsive to the ESD zap connected to the plurality of MOS transistors, operable to turn off the parasitic transistor after a selected period of time, whereby the energy of the ESD zap is expended.

2. The integrated circuit of claim 1, wherein the control circuit further comprises a latch circuit connected to the second bus and to the plurality of MOS transistors such that the latch is operable to be set when a voltage on the second bus exceeds a selected value in response to the ESD zap and the latch is further operable to be reset only when the voltage on the second bus falls to a value of within a safe operating range of the second supply voltage, such that the parasitic bipolar transistor is turned on in response to the latch circuit being set.

3. The integrated circuit of claim 1, wherein

the plurality of MOS transistors in the control circuit comprise a first PMOS transistor, a first NMOS transistor and a second PMOS transistor connected in cascode fashion, such that the first PMOS transistor has a source/drain connected to the second voltage bus, the second PMOS transistor has a source/drain connected to the reference supply bond pad and a control gate connected to the first voltage bus, and further comprising:

a capacitor with a first plate connected to a control gate of the first PMOS transistor and to a control gate of the first NMOS transistor and a second plate connected to the second voltage bus.

4. The integrated circuit of claim 1, wherein each diode in each respective local ESD protection circuitry is a portion of a respective output transistor of a respective output buffer.

5. A digital system comprising:

a first integrated circuit having an output buffer operable to provide and output signal on a first terminal having a first signal voltage level; and

a second integrated circuit having a plurality of signal bond pads, wherein an output buffer with a signal bond pad of the plurality of signal bond pads is connected to the first terminal;

the second integrated circuit comprising;

a semiconductor substrate connected to a bond pad for a reference supply voltage;

a first bus for a first supply voltage, and a second bus for a second supply voltage, wherein the second supply voltage is higher than the first supply voltage;

internal circuitry connected between the first bus and semiconductor substrate comprising MOS transistors having gate oxide with a first thickness suitable for the first supply voltage but not for the second supply voltage;

the plurality of signal bond pads for connecting to a respective plurality of external signals, wherein the plurality of external signals are operable at approximately the second supply voltage, with local ESD protection circuitry having a respective diode connected between each of the plurality of signal bond pads and the second bus; and

shared ESD circuitry connected between the second bus and the semiconductor substrate, wherein the shared ESD circuitry comprises;

at least one parasitic bipolar transistor with an emitter connected to the second bus and a collector connected to the semiconductor substrate with a base connected to a control circuit, wherein the control circuit comprises a plurality of MOS transistors each having gate oxide only of the first thickness such that the control circuit is operable to turn on the parasitic bipolar transistor in response to an ESD zap applied to any of the plurality of signal bond pads; and

wherein the control circuit further comprises an R/C timing circuit responsive to the ESD zap connected to the plurality of MOS transistors, operable to turn off the parasitic transistor after a selected period of time, whereby the energy of the ESD zap is expended.

6. A method for protecting an integrated circuit from an ESD pulse, wherein the integrated circuit has internal circuitry with transistors having gate oxide of a first thickness for operation at a first voltage and signal buffers designed to operate at a second voltage, the second voltage being higher than the first voltage, the method comprising the steps of:

receiving an ESD pulse on a signal pad of the integrated circuit;

diverting the ESD pulse from the signal bond pad to a shared ESD protection circuit via a voltage distribution bus for the second voltage within the integrated circuit;

sensing the ESD pulse with a plurality of MOS transistors connected in series between the voltage distribution bus and a reference substrate, wherein each of the plurality of MOS transistors has gate oxide of the first thickness;

turning on at least one parasitic bipolar transistor in the shared ESD protection circuit in response to the step of sensing;

dissipating the energy of the ESD pulse by conducting the ESD pulse through the at least one parasitic bipolar transistor while maintaining the at least one parasitic bipolar transistor in a conductive state for a selected period of time;

biasing the plurality of MOS transistors during normal operation of the integrated circuit such that the gate oxide of each of the plurality of MOS transistors is not subject to a voltage in excess of the first voltage; and

keeping the at least one parasitic bipolar transistor in a turned off state during normal operation of the integrated circuit in response to the biasing of the plurality of MOS transistors.

7. The method of claim 6, wherein the step of dissipating comprises maintaining the at least parasitic bipolar transistor in a conductive state until a voltage on the power distribution bus resulting from the ESD pulse decays to a safe value by timing a period of time after the onset of the ESD pulse.

8. The method of claim 6, wherein the step of dissipating comprises maintaining the at least one parasitic bipolar transistor in a conductive state until a voltage on the power distribution bus resulting from the ESD pulse decays to a safe value by comparing a voltage on the power distribution bus to a voltage on another node.