Reconfigurable processor devices

• US 6,353,841 B1
• Filed: 12/11/1998
• Issued: 03/05/2002
• Est. Priority Date: 12/17/1997
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Elixent Ltd. (Panasonic Holdings Corporation)
• Inventors: Stansfield, Anthony, Vuillemin, Jean, Marshall, Alan David
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US09/209,542
• Time in Patent Office: 1,180 Days
• Field of Search: 708/232, 708/230, 326/39, 326/38
• US Class Current: 708/232
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 7/527 in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel G06F7/533 takes precedence
• CPC Class Codes: G06F 7/53 in parallel-parallel fashion, i.e. both operands being entered in parallel G06F7/533 takes precedence
• CPC Class Codes: G06F 7/5338 each bitgroup having two new bits, e.g. 2nd order MBA
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/3897 with adaptable data path
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/1776 for memories

Abstract

The invention relates to a reconfigurable device comprising a plurality of processing devices, a connection matrix providing an interconnect between the processing devices, and means to define the configuration of the connection matrix. Each of the processing devices comprises an arithmetic logic unit, which is adapted to perform a function on input operands and produce an output. The input operands are provided as inputs to the arithmetic logic unit from the interconnect on the same route in each cycle. Dynamic instructions are enabled by means provided to route the output of a first one of the processing devices to a second one of the processing devices to determine the function performed by the second one of the processing devices.

Claims

1. A reconfigurable device comprising:

a plurality of processing devices;

a connection matrix providing an interconnect between the processing devices; and

means to define a configuration of the connection matrix;

wherein each of the processing devices comprises an arithmetic logic unit adapted to perform a function on input operands and produce an output, wherein said input operands are provided as inputs to the arithmetic logic unit from the interconnect on the same route in each cycle, and wherein the connection matrix is adapted to direct the output of a first one of the processing devices to a second one of the processing devices to determine the function performed by the second one of the processing devices.

2. A reconfigurable device as claimed in claim 1, wherein each of the processing devices contains no addressable input register, whereby input operands are received directly from the interconnect by the arithmetic logic unit.

3. A reconfigurable device as claimed in claim 1, wherein each of the processing devices has a first plurality of configuration bits which can be determined by the output of another one of the processing devices and a second plurality of configuration bits which cannot be determined by the output of another one of the processing devices.

4. A reconfigurable device as claimed in claim 1, wherein each of the processing devices has a first operand input, a second operand input, a function result output, a carry input and a carry output, wherein the first operand input, the second operand input and the function result output are n-bit, where n is an integer greater than 1, and the carry input and the carry output are 1-bit.

5. A reconfigurable device as claimed in claim 4, wherein n is equal to 4.

6. A reconfigurable device as claimed in claim 4, wherein each of the processing devices is adapted to receive, for determination of its function, an n-bit instruction input from another of the processing devices.

7. A reconfigurable device as claimed in claim 4, wherein means are provided to allow the carry input to one of the processing devices to change the function of the arithmetic logic unit of that processing device.

8. A reconfigurable device as claimed in claim 7, wherein said means allows the carry input to change the function of the arithmetic logic unit to its logical complement.

9. A reconfigurable device as claimed in claims 4, wherein means are provided for each of the processing devices to enable the carry input to be held at a constant value.

10. A reconfigurable device as claimed in claim 4, wherein a first one of the processing devices is usable to multiplex between two values of an instruction input to a second one of the processing devices according to the value of the carry input of the first of the processing devices.

11. A reconfigurable device as claimed in claim 10, wherein the carry input of the first of the processing devices can be propagated through the first of the processing devices to the carry input of the second of the processing devices.

12. A reconfigurable device as claimed in claim 1, wherein each of the processing devices comprises a latchable output register for the function output.

13. A reconfigurable device as claimed in claim 1, wherein each of the processing devices comprises a dynamic enable gate to determine whether instructions to determine the function of the arithmetic logic unit are to be accepted dynamically from the interconnect or are to be provided from configuration memory in the processing device.

14. A reconfigurable device as claimed in claim 1, wherein each of the processing devices comprises a dynamic instruction mask whereby application of the dynamic instruction mask to an instruction received by the processing device enables the instruction to provide both an instruction input to the arithmetic logic unit for determining the function of the arithmetic logic unit and a peripheral circuitry instruction input for control of peripheral circuitry in the processing device.

15. A method of constructing a central processing unit from a reconfigurable device, the reconfigurable device comprising a plurality of processing devices, a connection matrix providing an interconnect between the processing devices;

and means to define a configuration of the connection matrix, the method comprising;

allocating one or more of the processing devices to form an arithmetic logic unit of the central processing unit, wherein each of the processing devices comprises an arithmetic logic unit adapted to perform a function on input operands and produce an output, and wherein said input operands are provided as inputs to the arithmetic logic unit from the interconnect on the same route in each cycle;

associating a first memory, as a register file, with the arithmetic logic unit of the central processing unit; and

associating a second memory, as a code memory, with the arithmetic logic unit of the central processing unit, to provide instructions for the central processing unit, wherein instruction inputs for the arithmetic logic unit of the central processing unit are provided from the second memory.

16. A method as claimed in claim 15, wherein either or both of the first memory and the second memory are provided by reconfiguration of one or more parts of the reconfigurable device into memory available for use by the central processing unit configured onto the reconfigurable device.

17. A method as claimed in claim 16, wherein the one or more parts of the reconfigurable device comprise parts of the means to define the configuration of the connection matrix.

18. A method as claimed in claim 15, wherein the central processing unit has multiple arithmetic logic units, and wherein instructions for the multiple arithmetic logic units are provided from the second memory.

19. A method as claimed in claim 15, wherein instruction decoder circuitry is provided between the second memory and both the first memory and the arithmetic logic unit of the central processing unit, such that instructions may be stored in compressed form in the second memory and may be decoded by the instruction decoder circuitry before execution in the central processing unit.

20. A method as claimed in claim 19, wherein the central processing unit has multiple arithmetic logic units, wherein instructions for the multiple arithmetic logic units are provided from the second memory, and wherein common instruction decoder circuitry is provided for the multiple arithmetic logic units.

21. A method as claimed in claim 15, wherein each of the processing devices contains no addressable input register.

22. A method as claimed in claim 15, wherein each of the processing devices has a first plurality of configuration bits which can be determined by the output of another one of the processing devices and a second plurality of configuration bits which cannot be determined by the output of another one of the processing devices.

23. A method as claimed in claim 15, wherein each of the processing devices has a first operand input, a second operand input, a function result output, a carry input and a carry output, wherein the first operand input, the second operand input and the function result output are n-bit, where n is an integer greater than 1, and the carry input and the carry output are 1-bit.

24. A method as claimed in claim 23, wherein n is equal to 4.

25. A method as claimed in claim 23, wherein each of the processing devices is adapted to receive, for determination of its function, an n-bit instruction input from another of the processing devices.

26. A method as claimed in claim 23, wherein means are provided to allow the carry input to one of the processing devices to change the function of the arithmetic logic unit of that processing device.

27. A method as claimed in claim 26, wherein said means allows the carry input to change the function of the arithmetic logic unit to its logical complement.

28. A method as claimed in claim 23, wherein means are provided for each of the processing devices to enable the carry input to be held at a constant value.

29. A method as claimed in claim 23, wherein a first one of the processing devices is usable to multiplex between two values of an instruction input to a second one of the processing devices according to the value of the carry input of the first of the processing devices.

30. A method as claimed in claim 29, wherein the carry input of the first of the processing devices can be propagated through the first of the processing devices to the carry input of the second of the processing devices.

31. A method as claimed in claim 15, wherein each of the processing devices comprises a latchable output register for the function output.

32. A method as claimed in claim 15, wherein each of the processing devices comprises a dynamic enable gate to determine whether instructions to determine the function of the arithmetic logic unit are to be accepted dynamically from the interconnect or are to be provided from configuration memory in the processing device.

33. A method as claimed in claim 15, wherein each of the processing devices comprises a dynamic instruction mask whereby application of the dynamic instruction mask to an instruction received by the processing device enables the instruction to provide both an instruction input to the arithmetic logic unit for determining the function of the arithmetic logic unit and a peripheral circuitry instruction input for control of peripheral circuitry in the processing device.