Configurable encoder and method for generating a Reed-Solomon codeword

• US 6,353,909 B1
• Filed: 05/11/1999
• Issued: 03/05/2002
• Est. Priority Date: 05/11/1999
• Status: Expired due to Term

• Current Assignee: Ikanos Communications Incorporated (Qualcomm, Inc.)
• Original Assignee: Globespan Inc.
• Inventors: Pan, Wenwei, Santulli, William, Zheng, Yue-Peng, Amrany, Daniel
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US09/309,462
• Time in Patent Office: 1,029 Days
• Field of Search: 714/757, 714/784
• US Class Current: 714/757
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/158 Finite field arithmetic processing
• CPC Class Codes: H03M 13/6516 Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields

Abstract

Disclosed is a configurable Reed-Solomon encoder and method. The configurable Reed-Solomon encoder comprises a multiplexed multiplier-accumulator, a parallel latch bank operatively coupled to the multiplexed multiplier-accumulator, a data/parity multiplexer coupled to the parallel latch bank, and an encoder controller operatively coupled to, and controlling the operation of, the multiplexed multiplier-accumulator, the parallel latch bank, and the data/parity multiplexer. The configurable Reed-Solomon encoder is preferably implemented in an application specific integrated circuit (ASIC), although it may be implemented in software executed by a high-speed digital signal processor, etc.

Claims

1. A configurable Reed-Solomon encoder, comprising:

a multiplexed multiplier-accumulator further comprising a first adder and a second adder;

a parallel latch bank operatively coupled to the multiplexed multiplier-accumulator;

a data/parity multiplexer coupled to the parallel latch bank; and

an encoder controller operatively coupled to, and controlling the operation of, the multiplexed multiplier-accumulator, the parallel latch bank, and the data/parity multiplexer.

2. The encoder of claim 1, wherein the encoder is configurable to generate a user specified number of parity symbols for a user specified number of data symbols.

3. The encoder of claim 1, wherein the multiplexed multiplier-accumulator further comprises an RS coefficient generator circuit.

4. The encoder of claim 1, wherein the parallel latch bank further comprises:

a number of parallel latches, each parallel latch having a data input coupled to a distributed output of the multiplexed multiplier-accumulator;

a latch clock generator having a number of latching outputs, the latching outputs being coupled to a number of write enable inputs on the parallel latches, respectively; and

an output multiplexer having a number of multiplexer inputs, each of the multiplexer inputs being coupled to a data output of one of the parallel latches.

5. The encoder of claim 1, wherein the encoder controller further comprises a symbol correction input to configure the encoder to provide for the correction of a predetermined number of erroneous symbols t in a transmitted codeword.

6. The encoder of claim 1, wherein the encoder controller further comprises a codeword length input to configure the encoder to generate a number of codewords having n symbols.

7. The encoder of claim 1, wherein the encoder controller further comprises a code parameter type input to configure the encoder to perform a Reed/Solomon encoding function for one of at least two coefficient generation schemes.

8. A configurable Reed-Solomon encoder, comprising:

a multiplexed multiplier-accumulator;

a parallel latch bank operatively coupled to the multiplexed multiplier-accumulator;

a data/parity multiplexer coupled to the parallel latch bank; and

an encoder controller operatively coupled to, and controlling the operation of, the multiplexed multiplier-accumulator, the parallel latch bank, and the data/parity multiplexer, wherein the multiplexed multiplier-accumulator further comprises;

a coefficient generator;

a first adder having a feedback input coupled to the parallel latch bank and a data input;

a multiplier having a first input coupled to an output of the coefficient generator and a second input coupled to an output of the first adder;

a second adder having an input coupled to an output of the multiplier, a previous latch input coupled to the parallel latch bank, and an output coupled to the parallel latch bank.

9. A configurable Reed-Solomon encoder, comprising:

a multiplexed multiplier-accumulator;

a parallel latch bank operatively coupled to the multiplexed multiplier-accumulator;

a data/parity multiplexer coupled to the parallel latch bank; and

an encoder controller operatively coupled to, and controlling the operation of, the multiplexed multiplier-accumulator, the parallel latch bank, and the data/parity multiplexer, wherein the coupling between the parallel latch bank and the multiplexed multiplier-accumulator further comprises;

a feedback coupling;

a previous latch coupling; and

a distributed accumulator output coupling.

10. A configurable Reed-Solomon encoder, comprising:

a multiplexed multiplier-accumulator configured to generate a multiplier-accumulator output signal;

a parallel latch bank, the parallel latch bank being configured to generate a feedback output signal, a previous latch signal, and a latch bank output signal, the feedback output and the previous latch signals being applied to the multiplexed multiplier-accumulator, the multiplier-accumulator output signal being applied to the parallel latch bank;

a data/parity multiplexer configured to receive the latch bank output signal and a data signal, the data/parity multiplexer applying one of the latch bank output signal and the data signal to an encoder output; and

an encoder controller operatively coupled to, and controlling the operation of, the multiplexed multiplier-accumulator, the parallel latch bank, and the data/parity multiplexer.

11. A configurable Reed-Solomon encoder, comprising:

a multiplexed multiplier-accumulator;

parallel means for maintaining a number of parity symbols and for distributing an operation of the multiplexed multiplier-accumulator among the parity symbols;

means for toggling between a data symbol output and a parity symbol output; and

means for controlling the operation of the multiplexed multiplier-accumulator, the parallel means, and the data/parity multiplexer.

12. A method for generating a Reed-Solomon codeword, comprising the steps of:

generating a parity symbol output with a multiplexed multiplier-accumulator;

distributing the operation of the multiplexed multiplier-accumulator among a number of parallel latches; and

generating a data output from a data input and a number of parity symbols stored in the parallel latches.

13. The method of claim 12, further comprising the step of generating a number of Reed-Solomon polynomial coefficients.

14. The method of claim 12, wherein the step of distributing the operation of multiplier-accumulator further comprises the steps of:

applying the parity signal output of the multiplier-accumulator to a number of latches; and

selectively latching the parity signal output into the latches.

15. The method of claim 12, wherein the step of distributing the operation of the multiply accumulator further comprises the steps of:

applying the parity signal output of the multiply accumulator to a number of latches; and

selectively latching the parity signal output into the latches.