Three-dimensional chip stacking assembly

• US 6,355,501 B1
• Filed: 09/21/2000
• Issued: 03/12/2002
• Est. Priority Date: 09/21/2000
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Pogge, H. Bernhard, Fung, Ka Hing
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US09/666,767
• Time in Patent Office: 537 Days
• Field of Search: 438/107, 438/108, 438/109, 438/455, 438/458, 438/149, 438/151
• US Class Current: 438/107
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/81001 involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/81121 Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
• CPC Class Codes: H01L 2224/81141 Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

An assembly consisting of three dimensional stacked SOI chips, and a method of forming such integrated circuit assembly, each of the SOI chips including a handler making mechanical contact to a first metallization pattern making electrical contact to a semiconductor device. The metalized pattern, in turn, contacts a second metallization pattern positioned on an opposite surface of the semiconductor device. The method of fabricating the three-dimensional IC assembly includes the steps of: a) providing a substrate having a third metalized pattern on a first surface of the substrate; b) aligning one of the SOI chips on the first surface of the substrate, by having the second metallization pattern of the SOI chip make electrical contact with the third metalized pattern of the substrate; c) removing the handler from the SOI chip, exposing the first metallization pattern of the SOI chip; d) aligning a second one of the SOI chips with the first SOI chip, having the second metallization pattern of the second SOI chip make electrical contact to the exposed first metallization pattern of the first SOI chip; and e) repeating steps c) and d) for mounting subsequent SOI chips one on top of the other.

Claims

1. A method of fabricating a three-dimensional integrated circuit (IC) assembly, the assembly formed by a plurality of individual silicon-on-insulator (SOI) chips, each of the SOI chips comprising a handler making mechanical contact to a first metallization pattern, the first metallization pattern making electrical contact to a semiconductor device, the semiconductor device making an electrical connection to a second metallization pattern positioned on an opposite surface of the semiconductor device, the method of fabricating the three-dimensional IC assembly comprising the steps of:

a) providing a substrate having a third metalized pattern on a first surface of the substrate;

b) aligning one of the SOI chips on the first surface of the substrate, by having the second metallization pattern of the SOI chip make electrical contact with the third metalized pattern of the substrate;

c) removing the handler from the SOI chip, exposing the first metallization pattern of the SOI chip;

d) aligning a second one of the SOI chips with the first SOI chip, having the second metallization pattern of the second SOI chip make electrical contact to the exposed first metallization pattern of the first SOI chip; and

e) repeating steps c) and d) for mounting subsequent SOI chips one on top of each other.

2. The method as recited in claim 1, wherein the handler is provided with a layer of glue contacting the first metallization pattern of the SOI chip.

3. The method as recited in claim 2, wherein the handler and the glue material attached to the handler are transparent.

4. The method as recited in claim 3, wherein the SOI chips are aligned by optical means.

5. The method as recited in claim 4, wherein the SOI chips are aligned by capacitive means.

6. The method as recited in claim 4, wherein the SOI chips are first aligned by optical means to attain a rough alignment followed by a second alignment by way of capacitive means, thereby achieving a precise alignment of the stacked SOI chips.

7. The method as recited in claim 1, wherein the handler is removed by laser heating.

8. The method as recited in claim 1, further comprising the step of framing the assembly of mounted SOI chips with a vertical passivation layer positioned at each edge of the assembly of stacked SOI chips.

9. The method as recited in claim 1, wherein the bottommost one of the second metallization pattern of the SOI chip protrudes below the lower surface of the SOI chip, the protrusion having tapered edges.

10. The method as recited in claim 1, wherein the topmost first metallization pattern of the SOI chip or substrate, respectively, is indented below the top surface of the SOI chip or substrate, the indentation having tapered edges that match the tapered edges of the protrusion.

11. The method as recited in claim 9 further comprising the steps of:

a) forming solder bumps within the indented surface; and

b) fitting the protrusion within the indented surface, the fitting being conducted at a temperature above solder reflow, the fitting joining the protrusion, the indentation forming a single contact when the temperature returns to room temperature.

12. The method as recited in claim 9, wherein the indentation and the protrusion are provided with a tolerance allowing any misalignment between the SOI chips mounted on top of each other.