Three-dimensional packaging technology for multi-layered integrated circuits
First Claim
Patent Images
1. A module subassembly comprising:
- an element having a planar surface and at least an edge portion which is transparent to electromagnetic radiation;
a plurality of active circuit devices disposed in juxtaposition with said planar surface and spaced from said an edge portion; and
encoding means extending from a portion of said plurality of active circuit devices and terminating at the outer edge of said at least an edge portion.
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Abstract
Disclosed is method and apparatus for packaging multilayered integrated circuit (IC) chips, on which logic circuits and/or memory arrays are disposed and interconnected in a novel way permitting the addressing (i.e. selection) of the logic circuits and/or arrays on these IC chip layers using a minimum number of connections and with the shortest propagation delays.
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Citations
68 Claims
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1. A module subassembly comprising:
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an element having a planar surface and at least an edge portion which is transparent to electromagnetic radiation;
a plurality of active circuit devices disposed in juxtaposition with said planar surface and spaced from said an edge portion; and
encoding means extending from a portion of said plurality of active circuit devices and terminating at the outer edge of said at least an edge portion. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45)
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46. A three dimensional module assembly comprising:
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a plurality of elements each having a planar surface and at least an edge portion which is transparent to electromagnetic radiation, said elements and said edge portions being disposed in registry in a stack, each of said elements having a plurality of active circuit devices disposed in juxtaposition with said planar surface and spaced from said an edge portion, and, encoding means extending from a portion of said plurality of active circuit devices and terminating at the outer edge of said at least an edge portion of each of said elements. - View Dependent Claims (47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68)
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Specification