Semiconductor chip or device having a connecting member formed on a surface protective film

• US 6,355,977 B1
• Filed: 02/16/2000
• Issued: 03/12/2002
• Est. Priority Date: 02/18/1999
• Status: Expired due to Term

• Current Assignee: Achlys Technologies Inc.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Nakamura, Tomofumi
• Primary Examiner(s): Williams, Alexander O.
• Application Number:
  US09/504,856
• Time in Patent Office: 755 Days
• Field of Search: 252/777-781, 252/772, 252/738, 252/732, 252/734, 252/721, 252/758, 252/692, 252/693, 252/784, 252/786, 252/723, 252/686, 252/685, 252/774
• US Class Current: 257/693
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]

Abstract

A semiconductor chip which is joined to a surface of a solid such as a semiconductor chip or a wiring board. The semiconductor chip includes a surface protective film formed on its surface opposite to the surface of the solid, a connecting member formed on the surface protective film for electrically connecting the semiconductor chip and the solid to each other, and surface wiring for connecting internal wiring under the surface protective film and the connecting member to each other.

Claims

1. A semiconductor chip joined to a surface of a solid, comprising:

a surface protective film formed on a surface of the semiconductor chip that is opposite to the surface of the solid;

a connecting member formed on the surface protective film for supporting the semiconductor chip on the surface of the solid and electrically connecting the semiconductor chip and the solid to each other; and

surface wiring, formed on the surface protective film and exposed to the outside of the semiconductor chip, for connecting internal wiring formed under the surface protective film and the connecting member to each other.

2. The semiconductor chip according to claim 1, further comprising

a pad opening which is formed in the surface protective film for exposing a part of the internal wiring which is covered with the surface protective film,

the surface wiring connecting the internal wiring and the connecting member to each other through the pad opening.

3. The semiconductor chip according to claim 2, wherein

the connecting member is formed by stacking a seed film on a surface of the surface protective film having the pad opening formed therein and selectively plating the seed film, and

the surface wiring is formed by patterning the seed film.

4. The semiconductor chip according to claim 2, wherein

the surface wiring includes a first connecting portion connected to the internal wiring through the pad opening, a second connecting portion connected to the connecting member, and an intermediate portion formed on the surface of the surface protective film and connected to the first connecting portion and the second connecting portion.

8. A semiconductor chip according to claim 1, which further comprises an insulating film formed on an opposite side of said internal wiring relative to said surface protective film, and also between a semiconductor substrate and said surface protective film.

10. A semiconductor chip according to claim 8, wherein said insulating film includes an opening through which said internal wiring contacts said semiconductor substrate.

5. A semiconductor device of a chip-on-chip type constructed by opposing a surface of a first semiconductor chip to a surface of a second semiconductor chip to join the first and second semiconductor chips to each other, comprising:

a surface protective film formed on the surface, opposite to the second semiconductor chip, of the first semiconductor chip,

a connecting member formed between the surface protective film and the second semiconductor chip for electrically connecting the first and second semiconductor chips, and

surface wiring, formed on the surface protective film and exposed to the outside of the semiconductor chip, for connecting internal wiring formed under the surface protective film and the connecting member to each other.

6. The semiconductor device according to claim 5, wherein

a pad opening for exposing a part of the internal wiring which is covered with the surface protective film is formed in the surface protective film, and

the surface wiring connects the internal wiring and the connecting member to each other through the pad opening.

7. The semiconductor device according to claim 6, wherein

the surface wiring includes a first connecting portion connected to the internal wiring through the pad opening, a second connecting portion connected to the connecting member, and an intermediate portion formed on a surface of the surface protective film and connected to the first connecting portion and the second connecting portion.

9. A semiconductor device according to claim 5, which further comprises an insulating film formed on an opposite side of said internal wiring relative to said surface protective film, and also between a semiconductor substrate and said surface protective film.

11. A semiconductor device according to claim 9, wherein said insulating film includes an opening through which said internal wiring contacts said semiconductor substrate.