Dual die memory

• US 6,355,980 B1
• Filed: 07/15/1999
• Issued: 03/12/2002
• Est. Priority Date: 07/15/1999
• Status: Expired due to Fees

• Current Assignee: NanoAmp Solutions Incorporated
• Original Assignee: NanoAmp Solutions Incorporated
• Inventors: Callahan, John M.
• Primary Examiner(s): Cao, Phat Xuan
• Application Number:
  US09/354,288
• Time in Patent Office: 971 Days
• Field of Search: 257/734, 257/723, 257/686, 257/777, 257/778, 257/784
• US Class Current: 257/734
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01055 : Cesium [Cs]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A double-sized chip assembly and method is provided for two back-to-back integrated-circuit chips which both have the same fabrication mask sets. An electrically-selectable bonding-pad connection option alternatively provides a standard, non-reversed, option NRO for a bonding-pad layout and a non-standard, reversed option RO for the layout of the bonding-pads. The double-sized, back-to-back, wire-bonded integrated-circuit chip assembly and method includes a pair of integrated-circuit chips, each having one or more reversible wire-bonding-pads. One of the chips has its wire-bonding-pads electrically reversed such that the wire-bonding pads on both chips are located near each other to accommodate wire-bonding to a common bonding finger of a lead frame. A bonding-option wire-bonding-pad has an external voltage applied to it to indicate whether the integrated-circuit chip is to provide a standard pattern for the reversible wire-bonding-pads, or a reversed pattern for the reversible wire-bonding-pads. A voltage sensor circuit senses the voltage applied to the bonding-option wire-bonding-pad and alternatively generates either a standard NRO gate control signal or a non-standard, reversed RO gate control signal from the voltage state of the bonding-option wire-bonding-pad.

Claims

1. An integrated-circuit chip having one or more pairs of reversible wire-bonding-pads to alternatively provide a standard pattern for the reversible wire-bonding-pads and a non-standard, reversed wire-bonding pattern for the reversible wire-bonding-pads, comprising:

a first wire-bonding-pad;

a second wire-bonding-pad;

a first common signal line on said integrated-circuit chip;

a second common signal line on said integrated-circuit chip;

a first gate circuit having an input signal terminal connected to the first wire-bonding-pad, having an output signal terminal connected to the first common signal line, and having a control terminal which receives a standard wire-bonding configuration control signal which operates the first gate circuit to provide a standard pattern for the first wire-bonding-pad, which standard pattern connects the first wire-bonding-pad to the first common signal line to thereby provide the first input LOGIC signal to the first common signal line on said integrated-circuit chip;

a second gate circuit having an input signal terminal also connected to the first wire-bonding-pad, having an output signal terminal connected to the second common signal line, and having a control terminal which receives a non-standard, reversed wire-bonding configuration control signal which operates the second gate circuit to alternatively provide a non-standard, reversed pattern for the first wire-bonding-pad, which non-standard, reversed pattern connects the first wire-bonding-pad to the second common signal line to thereby alternatively provide the first input LOGIC signal to the second common signal line on said integrated-circuit chip;

a third gate circuit having an input signal terminal connected to the second wire-bonding-pad, having an output signal terminal connected to the second common signal line, and having a control terminal which receives the standard wire-bonding configuration control signal which operates the third gate circuit to provide a standard pattern for the second wire-bonding-pad, which standard pattern connects the second wire-bonding-pad to the second common signal line to thereby provide the second input LOGIC signal to the second common signal line on said integrated-circuit chip;

a fourth gate circuit having an input signal terminal also connected to the second wire-bonding-pad, having an output signal terminal connected to the first common signal line, and having a control terminal which receives the non-standard, reversed wire-bonding configuration control signal which operates the fourth gate circuit to alternatively provide a non-standard, reversed pattern for the second wire-bonding-pad, which non-standard, reversed pattern connects the second wire-bonding-pad to the first common signal line to thereby alternatively provide the second input LOGIC signal to the first common signal line on said integrated-circuit chip;

wherein the first gate circuit and the third gate circuit are controlled by the standard-bonding-pad control signal to provide a predetermined standard bonding-pad configuration for the integrated-circuit chip, which standard bonding-pad configuration connects the first wire-bonding input pad to the first common signal line on the integrated-circuit chip and which standard bonding-pad configuration also connects the second wire-bonding-pad to the second common signal line; and

whereby the second gate circuit and the fourth gate circuit are controlled by the reverse-bonding-pad control signal to provide a predetermined alternative reversed bonding-pad configuration for the integrated-circuit chip, which alternative reversed bonding-pad configuration connects the first wire-bonding-pad to the second common signal line and which alternative reversed bonding-pad configuration also connects the second wire-bonding-pad to first common signal line.

2. The integrated-circuit chip of claim 1, including

a plurality of pairs of first and second wire-bonding-pads;

a plurality of pairs of first and second common signal lines which are associated with one of said first and second wire bonding-pads;

a plurality of pairs of first and second gate circuits which are associated with one of said first and second wire bonding-pads;

a plurality of pairs of third and fourth gate circuits which are associated with one of said first and second wire bonding-pads; and

wherein each of said plurality of pairs of first and second wire-bonding-pads provides a standard pattern and a non-standard, reversed pattern for each of said plurality of pairs of wire-bonding-pads for the integrated-circuit chip.

3. The integrated-circuit chip of claim 1, including

a bonding-option wire-bonding-pad adapted to having an external voltage applied thereto to indicate whether the integrated-circuit chip is to provide a standard pattern for the reversible wire-bonding-pads, or alternatively, wither the integrated-circuit chip is to provide a reversed path for the reversible wire-bonding-pads;

a voltage sensor circuit for sensing the voltage applied to the bonding-option wire-bonding-pad and for alternatively generating either a standard NRO gate control signal or a non-standard, reversed RO gate control signal from the voltage state of the bonding-option wire-bonding-pad.

4. The integrated-circuit chip of claim 3, including

two or more bonding-option wire-bonding-pads, each of which are adapted to having an external voltage applied thereto;

one or more voltage sensor circuits for respectively sensing the voltage applied to a respective bonding-option wire-bonding-pad;

a bonding option logic signal array for generating one or more bonding option logic signals; and

a logic circuit for generating standard NRO and non-standard, reversed RO gate control signals from the one or more bonding option logic signals.

5. The integrated-circuit chip of claim 4, including three bonding-option wire-bonding-pads which are adapted to having an external voltage applied thereto such that the logic circuit for generating standard NRO and non-standard, reversed RO gate control signals generates the standard NRO and non-standard, reversed RO gate control signals.

6. The integrated-circuit chip of claim 1 wherein the gate circuits includes a logic circuit which has a first signal input terminal connected to one of the wire-bonding-pads, which has a second control signal input terminal which receives a wire-bonding configuration control signal to operate the gate circuit, and which has an output terminal coupled to one of the common signal lines.

7. The integrated-circuit chip of claim 6 wherein the gate circuits include a chip enable input terminal for receiving a chip enable signal CE to activate the gate circuits.

8. The integrated-circuit chip of claim 6:

wherein the logic circuit includes a first logic gate, having an input terminal connected to a first signal input terminal, having a second input terminal connected to the second control signal input terminal, and having an output terminal connected to an input terminal of the output driver circuit; and

wherein the logic circuit includes a second logic gate, having an input terminal connected through an inverter to the first signal input terminal, having a second input terminal connected through an inverter to the second control signal input terminal, and having an output terminal connected to an input terminal of the output driver circuit.

9. The integrated-circuit chip of claim 8 wherein the first logic gate includes a NAND gate and wherein the second logic gate includes a NOR gate.

10. The integrated-circuit chip of claim 9 wherein the first logic gate has an input terminal for receiving a chip enable signal CE and wherein the second logic gate has an input terminal for receiving an inverted chip enable signal.

11. The integrated-circuit chip of claim 9 wherein the logic circuit includes an output driver circuit having an input terminal and having an output terminal connected to one of the common signal lines.

12. The integrated-circuit chip of claim 11 wherein the output driver circuit includes a complementary-transistor output amplifier.

13. The integrated-circuit chip of claim 12 wherein the complementary transistor amplifier includes a p-channel transistor having a gate terminal connected to an output terminal of the NAND gate and a N-channel transistor connected to an output terminal of the NOR gate.

14. The integrated-circuit chip of claim 1 wherein the first and the second wire-bonding-pads are adapted to be connected to external control signals for the integrated-circuit chip.