Voltage boost circuit with low power supply voltage

• US 6,356,137 B1
• Filed: 06/26/2000
• Issued: 03/12/2002
• Est. Priority Date: 06/26/2000
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Roohparvar, Farzan, Mahouti, Kamyab
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Nguyen, Hai L.
• Application Number:
  US09/603,405
• Time in Patent Office: 624 Days
• Field of Search: 327/390, 327/530, 327/534, 327/535, 327/536, 327/538, 327/540, 327/547, 327/543, 327/589, 326/88, 307/110, 363/59, 363/60
• US Class Current: 327/390
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type

Abstract

Method and circuitry for efficiently boosting voltage for low power supply applications. In one embodiment a phase boosting circuit that boosts a clock signal to substantially twice the power supply voltage level in a single half-cycle is implemented. The circuit eliminates the need for depletion transistors and can thus be implemented using conventional complementary metal-oxide-semiconductor (CMOS) fabrication processes. A novel voltage summing circuit allows the phase doubler to achieve greater boosting capability for applications with ultra low power supply voltages.

Claims

1. A high voltage generating circuit having an input that receives an input signal and an output that provides a final boosted output signal, the high voltage generating circuit comprising:

a first voltage boosting circuit operable to generate a first boosted output signal in response to the input signal;

a second voltage boosting circuit operable to generate a second boosted output signal in response to the input signal; and

a summing circuit coupled to said first and second voltage boosting circuits configured to add voltage levels of said first boosted output signal and said second boosted output signal to generate the final boosted output signal, wherein the first voltage boosting circuit comprises;

a first pull-down transistor coupled between an output of the first voltage boosting circuit and a low potential and having an input coupled to the input of the high voltage generating circuit;

a first charge transfer transistor coupled between a first precharge node of the first voltage boosting circuit and the output of the first voltage boosting circuit and having an input coupled to the input of the high voltage generating circuit;

a first precharge transistor coupled between a power supply and the first precharge node and having an input coupled to the output of the first voltage boosting circuit;

a first capacitive element having a first terminal coupled to the first precharge node; and

a first inverter having an input coupled to the input of the high voltage generating circuit and an output coupled to a second terminal of the first capacitive element.

2. The high voltage generating circuit of claim 1, wherein a body terminal of the first charge transfer transistor couples to the first precharge node.

3. The high voltage generating circuit of claim 1, wherein a body terminal of the first precharge transfer transistor couples to the first precharge node.

4. The high voltage generating circuit of claim 1, wherein the first charge transfer transistor and the first precharge transistor are p-channel transistors, and the first pull-down transistor is an n-channel transistor.

5. The high voltage generating circuit of claim 4, wherein the power supply provides a positive power supply voltage, and the low potential is ground.

6. The high voltage generating circuit of claim 5, wherein the first inverter comprises a p-channel pull-up transistor coupled between the second terminal of the first capacitive element and the power supply, and an n-channel transistor coupled between the second terminal of the first capacitive element and ground.

7. The high voltage generating circuit of claim 1, wherein the first voltage boosting circuit boosts a voltage level of the input signal to a voltage that is at least twice the voltage level of the input signal.

8. The high voltage generating circuit of claim 7, wherein the first voltage boosting circuit is a phase doubler for a charge pump.

9. The high voltage generating circuit of claim 1, wherein the second voltage boosting circuit comprises:

a second pull-down transistor coupled between an output of the second voltage boosting circuit and a low potential and having an input coupled to the input of the high voltage generating circuit;

a second charge transfer transistor coupled between a second precharge node of the second voltage boosting circuit and the output of the second voltage boosting circuit and having an input coupled to the input of the high voltage generating circuit;

a second precharge transistor coupled between a power supply and the second precharge node and having an input coupled to the output of the second voltage boosting circuit;

a second capacitive element having a first terminal coupled to the second precharge node; and

a second inverter having an input coupled to the input of the high voltage generating circuit and an output coupled to a second terminal of the second capacitive element.

10. The high voltage generating circuit of claim 9, wherein a body terminal of the second charge transfer transistor couples to the second precharge node.

11. The high voltage generating circuit of claim 9, wherein a body terminal of the second charge transfer transistor couples to the second precharge node.

12. The high voltage generating circuit of claim 11, wherein the second inverter comprises a p-channel pull-up transistor coupled between the second terminal of the second capacitive element and the power supply, and an n-channel transistor coupled between the second terminal of the second capacitive element and ground.

13. A high voltage generating circuit, comprising:

a first voltage boosting circuit operable to generate a first boosted signal said first voltage boosting circuit having an input coupled to receive an input signal and an output;

a second voltage boosting circuit operable to generate a second boosted signal, said second voltage boosting circuit having an input coupled to receive the input signal and an output; and

a third voltage boosting circuit coupled to receive the first and second boosted signals, the third voltage boosting circuit operable to generate a third boosted signal that is greater in magnitude than those of the first and second boosted signals wherein each of the first, second and third boosting circuits comprises;

a pump capacitive element coupled between a first node and a precharge node;

a precharge transistor coupled between the precharge node and a power supply;

a charge transfer transistor coupled between the precharge node and the output; and

a pull-down transistor coupled between the output node and a discharge potential.

14. The high voltage generating circuit of claim 13, wherein gate terminals of the charge transfer and pull-down transistors in each of the first, second and third voltage boosting circuits are coupled to receive the input signal.

15. The high voltage generating circuit of claim 14, wherein a gate terminal of the precharge transistor in each of the first, second, and third voltage boosting circuits, respectively, couples to the output of its respective voltage boosting circuit.

16. The high voltage generating circuit of claim 15, wherein the third voltage boosting circuit further comprises a second pump capacitive element coupled between a second node and its precharge node, and

wherein, the first node and the second node in the third voltage boosting circuit couple to the outputs of the first voltage boosting circuit and the second voltage boosting circuit, respectively.

17. The high voltage generating circuit of claim 16, wherein each of the first and second voltage boosting circuits further comprises an inverter having an input coupled to receive the input signal and an output coupled to the first node in each of the respective voltage boosting circuits.

18. A method of generating a boosted voltage, comprising:

boosting an input signal using a first charge pump circuit to generate a first boosted signal;

boosting the input signal using a second charge pump circuit to generate a second boosted signal;

summing the first and second boosted signals; and

boosting a summed value of the first and second boosted signals using a third charge pump circuit to generate a boosted signal of larger magnitude,

wherein the summing function comprises capacitively coupling, in parallel, the first and the second boosted signals to the third charge pump circuit.