Arbitrary waveform generator having programmably configurable architecture

• US 6,356,224 B1
• Filed: 10/21/1999
• Issued: 03/12/2002
• Est. Priority Date: 10/21/1999
• Status: Expired due to Term

• Current Assignee: Xcerra Corporation (COHU Incorporated)
• Original Assignee: Credence Systems Corporation (COHU Incorporated)
• Inventors: Wohlfarth, Paul Dana
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): LAUTURE, JOSEPH J
• Application Number:
  US09/425,276
• Time in Patent Office: 873 Days
• Field of Search: 341/118, 341/120, 341/61, 341/143, 341/155
• US Class Current: 341/147
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06

Abstract

An arbitrary waveform generator (AWG) for producing an analog output current signal includes a random access memory (RAM), a programmable logic device (PLD), a programmable pattern generator, several digital-to analog converters (DACS) and a current multiplexer. The RAM store data sequences representing the analog waveform to be generated. The pattern generator read addresses the RAM causing it to sequentially read out its stored data sequence to the PLD. The PLD routes selected fields of each data sequence word to one or more of the DACs in response to timing signals provided by the pattern generator. Each DAC produces an output current of magnitude determined by its input waveform and range data. The pattern generator also signals the analog multiplexer to sum currents produced by one or more selected DACs to produce the AWG output waveform. The nature of the AWG output waveform is flexibly determined by the nature of the data sequence and the frequency at which it is read out of the RAM, the manner in which the PLD routes the data sequence to the DACs, the value of the range data supplied to each DAC, and the output pattern generated by the pattern generator. The flexible AWG architecture permits the AWG to be appropriately configured for various combinations of output waveform frequency, bandwidth and resolution requirements.

Claims

1. An arbitrary waveform generator (AWG) for producing an AWG output signal (IOUT), the AWG comprising:

a plurality of digital-to-analog converters (DACS) (20A-20D) for generating DAC output signals (IA-ID), each DAC output signal being of magnitude controlled by a waveform data field provided as input to the DAC generating it;

a memory (14) for storing and reading out a sequence of waveform data words (DOUT);

a programmable logic device (16) for processing said waveform data words read out of said memory to provide waveform data fields (DA-DD) as input to said DACs;

a pattern generator (18) for generating timing signals (T0-T4) supplied as input to said programmable logic device, and for generating control data, wherein said programmable logic device supplies each of said waveform data fields as input to said DACs in timed response to a separate one of said timing signals; and

signal processing means (22) for producing said AWG output signal in response to ones of said DAC output signals selected in response to said control data.

2. The AWG in accordance with claim 1

wherein said pattern generator also generates address data (ADDR) supplied as input to said memory, and

wherein said memory reads out said waveform data words in response to said address data.

3. The AWG in accordance with claim 1 wherein said pattern generator generates selection data (SEL) supplied as input to said signal processing means,

wherein said signal processing means sums current magnitudes of selected ones of said DAC output signals selected by said selection data to produce said AWG output signal.

4. The AWG in accordance with claim 1 wherein said programmable logic device processes said waveform data to produce said waveform data fields in response to configuration data (CONFIG DATA) provided as input to said programmable logic device.

5. An arbitrary waveform generator (AWG) for producing an AWG output signal (IOUT), the AWG comprising:

a plurality of digital-to-analog converters (DACS) (20A-20D) for generating DAC output signals (IA-ID);

a memory (14) for storing and reading out a sequence of waveform data words (DOUT);

a programmable logic device (16) for processing said waveform data words read out of said memory to provide a separate waveform data field as input to each of said DACs; and

signal processing means (22) for producing said AWG output signal in response to said DAC output signals;

wherein each of said DACs also receives input range data RA-RD), and

wherein a magnitude of the DAC output signal produced by each of said DACs is a function of a magnitude of its input range data and a magnitude of the waveform data field provided as input to the DAC.

6. The AWG in accordance with claim 5

wherein said signal processing means combines current magnitudes of said DAC output signals to produce said AWG output signal.

7. The AWG in accordance with claim 6 further comprising a pattern generator for generating selection data (SEL) supplied as input to said signal processing means,

wherein said signal processing means sums current magnitudes of selected ones of said DAC output signals selected by said selection data to produce said AWG output signal.

8. The AWG in accordance with claim 7 wherein said programmable logic device processes said waveform data to produce said waveform data fields in response to configuration data (CONFIG DATA) provided as input to said programmable logic device.

9. The AWG in accordance with claim 5 further comprising a pattern generator (18) for generating address data (ADDR) supplied as input to said memory, wherein said memory reads out said waveform data words in response to said address data.

10. The AWG in accordance with claim 5 further comprising a pattern generator for generating timing signals (T0-T4) supplied as input to said programmable logic device, wherein said programmable logic device supplies said waveform data fields as input to said DACs in timed response to said timing signals.

11. An arbitrary waveform generator (AWG) for producing an AWG output signal (IOUT), the AWG comprising:

a pattern generator (18) for generating an address field (ADDR) and a control field;

a plurality of digital-to-analog converters (DACS) (20A-20B) for generating DAC output signals, each DAC output signal being of magnitude controlled by a waveform data field (DA-DD) provided as input to the DAC generating it;

a memory (14) for storing and reading out a sequence of waveform data words (DOUT) in response to said address field;

a programmable logic device (16) for processing said waveform data words read out of said memory to provide said waveform data fields as input to said DACs; and

signal processing means (22) for producing said AWG output signal in response to said DAC output signals and said control field;

wherein said pattern generator also generates timing signals (T0-T4) supplied as input to said programmable logic device, and

wherein said programmable logic device supplies said waveform data fields as input to said DACs in timed response to said timing signals.

12. The AWG in accordance with claim 11 wherein said signal processing means sums current magnitudes of selected ones of said DAC output signals selected by said control field to produce said AWG output signal.

13. The AWG in accordance with claim 12 wherein said programmable logic device processes said waveform data to produce said waveform data fields in a manner controlled by configuration data (CONFIG DATA) provided as input to said programmable logic device.

14. The AWG in accordance with claim 11 wherein said address field (ADDR) and said control field (SEL) generated by said pattern generator are determined by pattern data provided as input to said pattern generator.

15. An arbitrary waveform generator (AWG) for producing an AWG output signal, the AWG comprising:

a plurality of digital-to-analog converters (DACS) (48A-48D) for generating DAC output signals (IA-ID), each DAC output signal being of magnitude controlled by a combination of a waveform data word input (DA-DD) and a range data word input (RA-RD) to the DAC generating it;

a plurality of memories (44), each for storing and reading out a separate sequence of data words;

a programmable logic device (46) for selectively routing said data words read out of said plurality of memories as waveform data word and range data word inputs to said plurality of DACs; and

signal processing means (45) for producing said AWG output signal in response to said DAC output signals.

16. The AWG in accordance with claim 15

wherein said signal processing means combines current magnitudes of said DAC output signals to produce said AWG output signal.

17. The AWG in accordance with claim 15 further comprising a pattern generator (48) for generating separate address data input (ADDR) supplied to each of said memories, wherein each of said memories reads out its sequence of data words in response to its address data input.

18. The AWG in accordance with claim 17 wherein said pattern generator generates selection data (SEL) supplied as input to said signal processing means, and

wherein said signal processing means sums current magnitudes of selected ones of said DAC output signals selected by said selection data to produce said AWG output signal.

19. The AWG in accordance with claim 15 wherein said programmable logic device selectively routes said data words read out of said plurality of memories as waveform data word and range data word inputs to said plurality of DACs in response to configuration data provided as input to said programmable logic device.

20. An arbitrary waveform generator (AWG) responsive to input configuration data, input pattern data, and a periodic clock signal for producing an AWG output signal, the AWG comprising:

a pattern generator programmed by the input pattern data for responding to the periodic clock signal by periodically generating a plurality of timing signals, addressing data, selection data and a read signal,

a memory addressed by the addressing data for periodically reading out waveform data in response to the read signal;

a programmable logic device configured by the input configuration data to process said waveform data to periodically generate a plurality of waveform data fields, each waveform data field being generated in timed response to a separate one of the timing signals;

a plurality of digital-to-analog converters (DACS), each receiving a separate one of the waveform data fields as an input and producing a separate DAC output signal having a magnitude that is a function of its input waveform data field; and

switch means for summing ones of the DAC output signals selected in response to the selection data to produce the AWG output signal.

21. The AWG in accordance with claim 20 further comprising means for supplying range data as another input to the DACs, wherein the DAC output signal produced by each DAC is of a magnitude that a function of the waveform data field and range data supplied as inputs to the DAC.

22. The AWG in accordance with claim 20 wherein the timing signals are of similar frequency and dissimilar phase.