Digital camera capable of converting a progressive scan signal into an interlace scan signal
First Claim
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1. A digital camera adapted to convert a progressive scan signal as an image signal into an interlace scan signal, comprising:
- a signal generator for outputting a progressive scan signal;
a memory for storing the progressive scan signal;
a bus for connecting said signal generator and said memory;
a controller for outputting a request signal that requests a release of said bus;
a CPU operative in response to the request signal to output a grant signal that grants a release of said bus;
a writer for responding to the grant signal to write the progressive scan signal into said memory; and
a reader for reading, out of said memory, an odd-numbered field related signal related to an odd-numbered field and an even-numbered field related signal related to an even-numbered field, wherein said memory includes a plurality of locations each of said locations having a plurality of bits, an input port for inputting the progressive scan signal and an output port for outputting the odd-numbered field related signal and the even-numbered field related signal.
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Abstract
A digital camera includes a CPU. The CPU releases a bus according to a bus-release request from a memory control circuit, and supplies a bus grant signal to the memory control circuit. Accordingly, the image data from a first signal processing circuit is written into a VRAM according to DMA. When the writing of the image is ended, the memory control circuit cancels the bus release request. The CPU accesses to the VRAM through the bus, to utilize the VRAM as a working memory.
31 Citations
22 Claims
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1. A digital camera adapted to convert a progressive scan signal as an image signal into an interlace scan signal, comprising:
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a signal generator for outputting a progressive scan signal;
a memory for storing the progressive scan signal;
a bus for connecting said signal generator and said memory;
a controller for outputting a request signal that requests a release of said bus;
a CPU operative in response to the request signal to output a grant signal that grants a release of said bus;
a writer for responding to the grant signal to write the progressive scan signal into said memory; and
a reader for reading, out of said memory, an odd-numbered field related signal related to an odd-numbered field and an even-numbered field related signal related to an even-numbered field, wherein said memory includes a plurality of locations each of said locations having a plurality of bits, an input port for inputting the progressive scan signal and an output port for outputting the odd-numbered field related signal and the even-numbered field related signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A digital camera adapted to convert a progressive scan signal as an image signal into an interlace scan signal, comprising:
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a signal generator for outputting a progressive scan signal;
a memory for storing the progressive scan signal;
a bus for connecting said signal generator and said memory;
a controller for outputting a request signal that requests a release of said bus;
a CPU operative in response to the request signal to output a grant signal that grants a release of said bus;
a writer for responding to the grant signal to write the progressive scan signal into said memory; and
a reader for reading, out of said memory, an odd-numbered field related signal related to an odd-numbered field and an even-numbered field related signal related to an even-numbered field, wherein said writer writes the progressive scan signal at a first high-speed clock rate, that is more than twice a reference clock rate, into said memory, and said reader separately reads the odd-numbered field related signal and the even-numbered field related signal at a second high-speed clock rate, that is more than twice the reference clock rate, from said memory. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A digital camera, comprising:
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an image sensor;
an image data generator for outputting image data based on an image signal from said image sensor;
a memory having a plurality of memory locations each configured by a plurality of bits, and an input port and an output port correspondingly connected to a writing bus and a reading bus;
a CPU;
an interconnection bus for connecting an output of said image data generator, said writing bus and said CPU;
a memory controller for outputting a bus release request to said CPU to write the image data from said image data generator through said interconnection bus to said memory; and
an output circuit for processing the image data outputted from said reading bus; and
wherein;
said image data generator outputs 1 frame of image data including an odd-numbered line and an even-numbered line;
one of the odd-numbered line and the even-numbered line of the image data being stored into higher-order bits of one of said memory locations and the other of the odd-numbered line and the even-numbered line of the image data being stored into lower-order bits thereof; and
the image data in the higher-order bits and the lower-order bits of said one memory location being simultaneously read out and supplied through said reading bus to said output circuit. - View Dependent Claims (20, 21, 22)
said image sensor has a color filter having a same color arrangement repeated on every two lines; - and
said output circuit has an RGB signal creating circuit for creating an RGB signal by utilizing the image data of the odd-numbered line and the even-numbered line simultaneously applied thereto.
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21. A digital camera according to claim 19, further comprising a non-volatile RAM connected to said CPU, wherein said CPU accesses said memory through said interconnection bus so as to create and write compressed luminance data and compressed chrominance data based on the image data into said non-volatile RAM.
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22. A digital camera according to claim 21, wherein said CPU reads out, from the non-volatile RAM, and expands the compressed luminance data and the compressed chrominance data and stores expanded luminance data into one of the higher-order bits and the lower-order bits of the one memory location and expanded chrominance data into the other of the higher-order bits and the lower-order bits thereof;
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said output circuit has a pseudo frame signal creator for creating a pseudo frame signal based on the expanded luminance data and the expanded chrominance data read out of said memory through said reading bus.
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Specification