Image synthesizing device and image conversion device for synthesizing and displaying an NTSC or other interlaced image in any region of a VCA or other non-interlaced image

• US 6,356,314 B1
• Filed: 09/09/1999
• Issued: 03/12/2002
• Est. Priority Date: 03/10/1997
• Status: Expired due to Fees

• Current Assignee: Komatsu Ltd.
• Original Assignee: Komatsu Ltd.
• Inventors: Takebe, Makoto
• Primary Examiner(s): HSIA, SHERRIE Y
• Application Number:
  US09/380,811
• Time in Patent Office: 915 Days
• Field of Search: H04/N.5445, H04/N.545, 348/563, 348/564, 348/565, 348/567, 348/568, 348/584, 348/586, 348/588, 348/598, 348/448
• US Class Current: 348/564
• CPC Class Codes: G09G 2310/0229 De-interlacing
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/397 Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay G09G5/02 takes precedence
• CPC Class Codes: H04N 5/45 Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 7/012 Conversion between an interlaced and a progressive signal for graphics images G09G2310/0229
• CPC Class Codes: H04N 9/641 Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence

Abstract

Provided is an image synthesizing device with which a specific display region P of a sub-image is synthesized and displayed within a specific display region Q of a main image displayed on a display 9, wherein this image synthesizing device comprises a frame memory with which the data in the synthesis and display region P out of the sub-image data is continuously stored in the order of input, after which the stored sub-image data is read out when the scanning address of the main image data is an address corresponding to the display region Q, and a selector 4 with which the main image data displayed on the display 9 and the sub-image data continuously and sequentially read out from the frame memory are inputted, and when the scanning address of the main image data is an address corresponding to the display region Q, the selected channel is switched from main image data to the sub-image data and outputted to the display 9 where this sub-image data is displayed, which allows the capacity of the frame memory used for image synthesis to be smaller, and allows the sub-image to be reduced or magnified at the desired scale factor.

Claims

1. An image synthesizing device with which a sub-image included in a specific extraction region of an interlaced scan sub-image composed of odd-numbered fields and even-numbered fields is synthesized and displayed within a specific display region of a non-interlaced scan main image displayed on a display, comprising:

a first frame memory with which write and read operations can be performed asynchronously and which stores data for odd-numbered fields out of the sub-image in an address region specified by an address signal;

a second frame memory with which write and read operations can be performed asynchronously and which stores data for even-numbered fields out of the sub-image in an address region specified by the address signal;

write control means for packing and sequentially storing data for odd-numbered fields out of that data within the extraction region to be synthesized out of the sub-image, in a continuous address region of the first frame memory in the order of extraction from the extraction region, and for packing and sequentially storing data for even-numbered fields out of that data within the extraction region to be synthesized out of the sub-image, in a continuous address region of the second frame memory in the order of extraction from the extraction region;

read control means for alternately reading the sub-image data stored in the first and second frame memories in the order of the address when the scanning address of the main image data corresponds to being within the display region of the main image; and

selection means for selecting the main image data when the scanning address of the main image data is outside the display region of the main image, selecting the sub-image data sequentially read from the first and second frame memories when the scanning address of the main image data is within the display region of the main image, and outputting the selected data to the display.

2. The image synthesizing device according to claim 1, wherein, when the extraction region of the sub-image is reduced to a specific scale factor and synthesized and displayed in the display region of the main image, the first and second frame memories thin lines in a vertical direction to a specific scale factor when the scanning address of the sub-image data at a time of sub-image data input corresponds to the display region, and stores the sub-image data which have been inputted after being horizontally thinned out to the specific scale factor when the scanning address in the horizontal direction corresponds to the display region for each of these thinned-out lines, after which the thinned-out and stored sub-image data is continuously read out in the order of the input when the scanning address of the main image data corresponds to the display region of the main image.

3. The image synthesizing device according to claim 1, wherein a line buffer FIFO is provided with which, after the sub-image data read from the first and second frame memories has been inputted and then stored in the order of input, the stored sub-image data is read out in the order of input;

when the extraction region of the sub-image is magnified to a specific scale factor and synthesized and displayed in the display region of the main image, the first and second frame memories continuously store only that data out of the sub-image data that is within the extraction region in the inputted order, after which one line of data out of the stored sub-image data is read out at a cycle reduced to the specific scale factor with respect to a frequency of a horizontal dot clock of the main image one line at a time for a specific number of lines corresponding to the specific scale factor when the scanning address of the main image data corresponds to the display region of the main image; and

the line buffer FIFO stores this one line of read sub-image data synchronously with the horizontal dot clock of the main image in the inputted order, after which the stored one line of sub-image data is repeatedly outputted for each line in the input order for remaining lines of the specific lines corresponding to the specific scale factor of the display region of the main image data.

4. The image synthesizing device according to claim 3, wherein the line buffer FIFO stores one line of the sub-image data read from the first and second frame memories at a cycle reduced to the specific scale factor with respect to the frequency of the horizontal dot clock of the main image in the inputted order, after which one line of the stored sub-image data is read out at a cycle reduced to the specific scale factor with respect to the frequency of the horizontal dot clock of the main image in the inputted order for the remaining lines of the specific lines corresponding to the specific scale factor of the display region of the main image data, and is repeatedly outputted for each line.

5. An image conversion device which converts interlaced scan image signals composed of odd-numbered fields and even-numbered fields into non-interlaced scan image signals, comprising:

one serial access memory with which write and read operations can be performed asynchronously and which sequentially stores interlaced scan image signals in an address region incremented synchronously with inputted clock signals;

write clock formation means for extracting control-use synchronization signals from inputted interlaced scan image signals and forming write-use clock signals with respect to the serial access memory on the basis of the extracted signals;

high-speed clock signal generation means for generating high-speed clock signals with a higher frequency than the write-use clock signals;

first write control means for storing the image data of one of the fields in an intermittent address region of the serial access memory corresponding to an order of lines in the one field by alternately executing a first operation, in which one line of interlaced scan image data is written while the write address of the serial access memory is incremented synchronously with the write-use clock signals when image data of one of the fields of the interlaced scan image signals has been inputted, and a second operation, in which the write address of the serial access memory is incremented by an amount equal to the address region corresponding to one line of image data synchronously with the high-speed clock signals without data writing being performed, with a specific address of the serial access memory serving as a first origin address;

second write control means for storing, corresponding to an order of lines in the other field, image data of the other field in empty address regions formed between the address regions where the image of the lines of the one field of the serial access memory is stored by alternately executing a third operation, in which one line of interlaced scan image data is written while the write address of the serial access memory is incremented synchronously with the write-use clock signals when image data of the other field of the interlaced scan image signals has been inputted, and a fourth operation, in which the write address of the serial access memory is incremented by an amount equal to the address region corresponding to one line of image data synchronously with the high-speed clock signals without data writing being performed, with a second origin address advanced by an address region corresponding to one line of image data from the first origin address serving as the origin; and

read control means for reading, in the address order from the first origin address, the interlaced scan image data stored in the serial access memory by the first and second write control means;

and wherein one frame of interlaced scan image signals are packed and stored in a continuous address region of the serial access memory.

6. An image synthesizing device with which a sub-image included in a specific extraction region of an interlaced scan sub-image composed of odd-numbered fields and even-numbered fields is synthesized and displayed within a specific display region on a display screen on which a non-interlaced scan main image is displayed, comprising:

one serial access memory with which write and read operations can be performed asynchronously and which sequentially stores sub-image signals in an address region which is advanced synchronously with inputted clock signals;

write clock formation means for extracting control-use synchronization signals from inputted sub-image signals and forming write-use clock signals with respect to the serial access memory on the basis of the extracted signals;

high-speed clock signal generation means for generating high-speed clock signals with a higher frequency than the write-use clock signals;

first write control means for storing the image data to be displayed in the display region of one of the fields out of the sub-image signals in an intermittent address region of the serial access memory corresponding to an order of lines in the one field by alternately executing a first operation, in which one line of data to be displayed in the display region of the one field is written while the write address of the serial access memory is incremented synchronously with the write-use clock signals when an image of the one field has been inputted and when the sub-image included in the specific extraction region has been inputted, and a second operation, in which the write address of the serial access memory is incremented by an amount equal to the address region corresponding to one line of sub-image data to be displayed in the display region synchronously with the high-speed clock signals without data writing being performed, with a specific address of the serial access memory serving as a first origin address;

second write control means for storing, corresponding to an order of lines in the other field out of the sub-image signals, the image data to be displayed in the display region of the other field in empty address regions formed between the address regions where the image of the lines of the one field of the serial access memory is stored by alternately executing a third operation, in which one line of data to be displayed in the display region of the other field is written while the write address of the serial access memory is incremented synchronously with the write-use clock signals when an image of the other field has been inputted and when the sub-image included in the specific extraction region has been inputted, and a fourth operation, in which the write address of the serial access memory is incremented by an amount equal to the address region corresponding to one line of sub-image data to be displayed in the display region synchronously with the high-speed clock signals without data writing being performed, with an origin address being a second origin address advanced from the first origin address by an amount equal to the address region corresponding to one line of image data to be displayed in the display region;

read control means for reading, in the address order from the first origin address, the sub-image data stored in the serial access memory by the first and second write control means when the scanning address of the main image is an address corresponding to the specific display region; and

switching means for selecting the main image when the scanning address of the main image is not an address corresponding to the specific display region, and selecting and outputting the sub-image outputted from the serial access memory when the scanning address of the main image is an address corresponding to the specific display region;

and wherein one frame of interlaced scan image signals are packed and stored in a continuous address region of the serial access memory.

7. The image synthesizing device according to claim 6, further comprising:

reduction factor setting means for setting a reduction factor of the sub-image; and

display region setting means for setting a reduction of the display region in which the sub-image is displayed on the display screen according to the reduction factor set by the reduction factor setting means;

wherein the first write control means, in a course of the execution of the first operation, thins the sub-image of one of the fields included in the specific extraction region in a main scanning direction and a sub-scanning direction according to the set reduction factor, and in a course of the execution of the second operation, increments the write address of the serial access memory by an amount equal to the address region corresponding to one line of reduced sub-image data to be displayed in the display region;

the second write control means, in a course of the execution of the third operation, thins the sub-image of the other field included in the specific extraction region in the main scanning direction and the sub-scanning direction according to the set reduction factor, and in a course of the execution of the fourth operation, increments the write address of the serial access memory by an amount equal to the address region corresponding to one line of reduced sub-image data to be displayed in the display region, and alternately executes these third and fourth operations, with the second origin address being an address advanced from the first origin address by an amount equal to the address region corresponding to one line of reduced image data to be displayed in the display region;

the read control means reads the sub-image data stored in the serial access memory by the first and second write control means in the address order from the first origin address when the scanning address of the main image is an address corresponding to the display region reduced by the display region setting means; and

the switching means selects the main image when the scanning address of the main image is not an address corresponding to the display region reduced by the display region setting means, and selects and outputs the sub-image outputted from the serial access memory when the scanning address of the main image is an address corresponding to the display region reduced by the display region setting means.

8. An image conversion device which converts interlaced scan image signals composed of odd-numbered fields and even-numbered fields into non-interlaced scan image signals, comprising:

one video memory with which write and read operations can be performed asynchronously and which sequentially stores interlaced scan image signals in an address region corresponding to inputted address signals;

first write control means for storing the image data of one of the fields in an intermittent address region of the video memory corresponding to an order of lines in the one field by alternately executing a first operation, in which one line of interlaced scan image data is written while the write address of the video memory is advanced when image data of one of the fields of the interlaced scan image signals has been inputted, and a second operation, in which the write address of the video memory is skipped by an amount equal to the address region corresponding to one line of image data without data writing being performed, with a specific address of the video memory serving as a first origin address;

second write control means for storing, corresponding to an order of lines in the other field out of the sub-image signals, image data of the other field in empty address regions formed between the address regions where the image of the lines of the one field of the video memory is stored by alternately executing a third operation, in which one line of interlaced scan image data is written while the write address of the video memory is advanced when an image of the other field has been inputted, and a fourth operation, in which the write address of the video memory is skipped by an amount equal to the address region corresponding to one line of image data without data writing being performed, with the origin being a second origin address advanced from the first origin address by an amount equal to the address region corresponding to one line of image data; and

read control means for reading, in the address order from the first origin address, the interlaced scan image data stored in the video memory by the first and second write control means;

and wherein one frame of interlaced scan image signals are packed and stored in a continuous address region of the video memory.

9. An image synthesizing device with which a sub-image included in a specific extraction region of an interlaced scan sub-image composed of odd-numbered fields and even-numbered fields is synthesized and displayed within a specific display region on a display screen on which a non-interlaced scan main image is displayed, comprising:

one video memory with which write and read operations can be performed asynchronously and which sequentially stores sub-image signals in an address region corresponding to inputted address signals;

first write control means for storing the image data to be displayed in the display region of one of the fields out of the sub-image signals in an intermittent address region of the video memory corresponding to an order of lines in the one field by alternately executing a first operation, in which one line of data to be displayed in the display region of the one field is written while the write address of the video memory is advanced when an image of the one field has been inputted and when the sub-image included in the specific extraction region has been inputted, and a second operation, in which the write address of the video memory is skipped by an amount equal to the address region corresponding to one line of sub-image data to be displayed in the display region without data writing being performed, with a specific address of the video memory serving as a first origin address;

second write control means for storing, corresponding to an order of lines in the other field out of the sub-image signals, image data to be displayed in the display region of the other field in empty address regions formed between the address regions where the image of the lines of the one field of the video memory is stored by alternately executing a third operation, in which one line of data to be displayed in the display region of the other field is written while the write address of the video memory is advanced when an image of the other field has been inputted and when the sub-image included in the specific extraction region has been inputted, and a fourth operation, in which the write address of the video memory is skipped by an amount equal to the address region corresponding to one line of sub-image data to be displayed in the display region without data writing being performed, with the origin being a second origin address advanced from the first origin address by an amount equal to the address region corresponding to one line of image data to be displayed in the display region;

read control means for reading, in the address order from the first origin address, the sub-image data stored in the video memory by the first and second write control means when the scanning address of the main image is an address corresponding to the specific display region; and

switching means for selecting the main image when the scanning address of the main image is not an address corresponding to the specific display region, and selecting and outputting the sub-image outputted from the video memory when the scanning address of the main image is an address corresponding to the specific display region;

and wherein one frame of interlaced scan image signals are packed and stored in a continuous address region of the video memory.

10. The image synthesizing device according to claim 9, further comprising:

reduction factor setting means for setting a reduction factor of the sub-image; and

display region setting means for setting a reduction of the display region in which the sub-image is displayed on the display screen according to the reduction factor set by the reduction factor setting means;

wherein the first write control means, in a course of the execution of the first operation, thins the sub-image of one of the fields included in the specific extraction region in a main scanning direction and a sub-scanning direction according to the set reduction factor, and in a course of the execution of the second operation, skips the write address of the video memory by an amount equal to the address region corresponding to one line of reduced sub-image data to be displayed in the display region;

the second write control means, in a course of the execution of the third operation, thins the sub-image of the other field included in the specific extraction region in the main scanning direction and the sub-scanning direction according to the set reduction factor, and in a course of the execution of the fourth operation, skips the write address of the video memory by an amount equal to the address region corresponding to one line of reduced sub-image data to be displayed in the display region, and alternately executes these third and fourth operations, with the second origin address being an address advanced from the first origin address by an amount equal to the address region corresponding to one line of reduced image data to be displayed in the display region;

the read control means reads the sub-image data stored in the video memory by the first and second write control means in the address order from the first origin address when the scanning address of the main image is an address corresponding to the display region reduced by the display region setting means; and

the switching means selects the main image when the scanning address of the main image is not an address corresponding to the display region reduced by the display region setting means, and selects and outputs the sub-image outputted from the video memory when the scanning address of the main image is an address corresponding to the reduced display region.

11. The image synthesizing device according to claim 9, wherein the video memory comprises:

random access memory means allowing write and read operations to be performed asynchronously and for sequentially storing sub-image signals written by the first and second write control means;

serial access memory means for temporarily storing at least one line of sub-image signals by data transfer from the random access memory means; and

first read control means for performing data read control from the serial access memory means on the basis of inputted serial clock signals;

read clock formation means is provided for extracting control-use synchronization signals from inputted main image signals and forming read-out clock signals with respect to the video memory on the basis of the extraction signals;

the display screen on which the main image is displayed performing a display operation synchronously with the read clock signals;

magnification factor setting means is provided for setting a magnification factor M; and

display region setting means is provided for setting the magnification of the display region in which the sub-image is displayed on the display screen according to the magnification factor M set by the magnification factor setting means;

the read control means comprises;

address generation means for generating addresses increased by an amount of address skipped by the first and second write control means once for every M-number of sub-scans of the main image, with an initial value being the first origin address of the random access memory means;

second read control means for causing the data transfer to be performed, with an output address of the address generation means being a transfer start address, at least once for every M-number of sub-scans of the main image when the sub-scanning address of the main image is an address corresponding to the display region magnified by the display region setting means;

main scanning direction magnification means for causing data corresponding to the amount of address skipped by the second write control means to be outputted at a frequency of 1/M that of the read clock signals out of the sub-image signals stored temporarily in the serial access memory means when the scanning address of the main image is an address corresponding to the display region magnified by the display region setting means; and

sub-scanning direction magnification means for outputting the sub-image signals temporarily stored in the serial access memory means continuously for M times and synchronously with the sub-scanning of the main image when the scanning address of the main image is an address corresponding to the display region magnified by the display region setting means;

and wherein the switching means selects the main image when the scanning address of the main image is not an address corresponding to the display region magnified by the display region setting means, and selects and outputs the sub-image outputted from the video memory when the scanning address of the main image is an address corresponding to the display region magnified by the display region setting means.

12. An image synthesizing device with which a sub-image included in a specific extraction region of a sub-image is synthesized and displayed within a specific display region of a main image displayed on a display, comprising:

a frame memory with which write and read operations can be performed asynchronously and which stores sub-image data in an address region specified by an address signal, and when the extraction region of the sub-image is reduced to a specific scale factor and synthesized and displayed in the display region of the main image, the frame memory thins lines in a vertical direction to a specific scale factor when the scanning address of the sub-image data at a time of sub-image data input corresponds to the display region, and stores the sub-image data which have been inputted after being horizontally thinned out to the specific scale factor when the scanning address in the horizontal direction corresponds to the display region for each of these thinned-out lines, after which the thinned-out and stored sub-image data is continuously read out in the order of the input when the scanning address of the main image data corresponds to the display region of the main image;

write control means for packing and sequentially storing that data within the extraction region to be synthesized out of the sub-image, in a continuous address region of the frame memory in an order of extraction from the extraction region;

read control means for sequentially reading the sub-image data stored in the frame memory in an order of the address when a scanning address of the main image data corresponds to being within the display region of the main image; and

selection means for selecting the main image data when the scanning address of the main image data is outside the display region of the main image, selecting the sub-image data sequentially read from the frame memory when the scanning address of the main image data is within the display region of the main image, and outputting the selected data to the display.

13. An image synthesizing device with which a sub-image included in a specific extraction region of a sub-image is synthesized and displayed within a specific display region of a main image displayed on a display, comprising:

a frame memory with which write and read operations can be performed asynchronously and which stores sub-image data in an address region specified by an address signal;

write control means for packing and sequentially storing that data within the extraction region to be synthesized out of the sub-image, in a continuous address region of the frame memory in an order of extraction from the extraction region;

read control means for sequentially reading the sub-image data stored in the frame memory in an order of the address when a scanning address of the main image data corresponds to being within the display region of the main image;

selection means for selecting the main image data when the scanning address of the main image data is outside the display region of the main image, selecting the sub-image data sequentially read from the frame memory when the scanning address of the main image data is within the display region of the main image, and outputting this selected data to the display; and

a line buffer FIFO is provided with which, after the sub-image data read from the frame memory has been inputted and then stored in the order of input, the stored sub-image data is read out in the order of input;

wherein, when the extraction region of the sub-image is magnified to a specific scale factor and synthesized and displayed in the display region of the main image, the frame memory continuously stores only that data out of the sub-image data that is within the extraction region in the inputted order, after which one line of data out of the stored sub-image data is read out at a cycle reduced to the specific scale factor with respect to a frequency of a horizontal dot clock of the main image one line at a time for a specific number of lines corresponding to the specific scale factor when the scanning address of the main image data corresponds to the display region of the main image; and

the line buffer FIFO stores this one line of read sub-image data synchronously with the horizontal dot clock of the main image in the inputted order, after which the stored one line of sub-image data is repeatedly outputted for each line in the input order for remaining lines of the specific lines corresponding to the specific scale factor of the display region of the main image data.