Apparatus and method for an integrated photodiode in an infrared receiver

• US 6,356,375 B1
• Filed: 03/10/1998
• Issued: 03/12/2002
• Est. Priority Date: 03/27/1997
• Status: Expired due to Term

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Integration Associates, Inc. (Silicon Laboratories Incorporated)
• Inventors: Holcombe, Wayne T.
• Primary Examiner(s): Chan, Jason
• Assistant Examiner(s): Bello, Agustin
• Application Number:
  US09/041,062
• Time in Patent Office: 1,463 Days
• Field of Search: 359/189, 359/193, 359/194
• US Class Current: 398/209
• CPC Class Codes: H03G 3/3084 in receivers or transmitters for electromagnetic waves other than radiowaves, e.g. lightwaves H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H04B 10/11 Arrangements specific to free-space transmission, i.e. transmission through air or vacuum

Abstract

A method and apparatus are shown for integrating a photodiode and a receiver circuit on a single substrate. An input signal is received with the photodiode. The receiver circuit is configured to suppress feedback from an output terminal of the receiver circuit to the photodiode by amplifying the input signal to produce an amplified input signal, controlling the gain of the input signal amplification responsive to the magnitude of the amplified input signal, comparing the amplified input signal to a detection threshold voltage to produce a digital data signal, and holding the gain at a substantially constant level in response to a fast signal transition in the digital output signal.

Claims

1. An integrated photodiode and receiver circuit on a substrate, the integrated receiver circuit comprising:

a first diffused region in the substrate for receiving an input signal;

a first circuit input terminal coupled to the first diffused region;

a circuit output terminal;

an input amplifier interposed between the first circuit input and receiver output terminals, the input amplifier being configured to receive and amplify the input signal to produce an amplified input signal, and wherein the input amplifier is further configured to vary the gain of the input amplifier responsive to a gain control signal;

a bandpass filter interposed between the input amplifier and the circuit output terminal, the bandpass filter being configured to receive and bandpass filter the amplified input signal so as to produce a filtered input signal;

a comparator interposed between the bandpass filter and the circuit output terminal, the comparator being configured to compare the filtered input signal to a detection threshold voltage level in order to generate a digital output signal;

a delay circuit interposed between the comparator and the circuit output terminal, the delay circuit being configured to receive the digital output signal and generate a delayed digital output signal responsive thereto;

an automatic gain control circuit configured to receive the filtered input signal, the automatic gain control circuit comparing the filtered input signal to an automatic gain control threshold voltage and generating the gain control signal responsive thereto;

an isolation control signal generator configured to receive the delayed digital output signal and generating an isolation control signal responsive thereto; and

an isolation switch interposed between the input amplifier and the automatic gain control circuit, the isolation switch being configured to receive the isolation control signal and, responsive thereto, isolate the automatic gain control circuit from the amplified input signal.

2. The integrated receiver circuit of claim 1 wherein the isolation switch is further configured to isolate the comparator from the amplified input signal responsive to the isolation control signal.

3. The integrated receiver circuit of claim 1 wherein the isolation switch is further configured to isolate the bandpass filter from the amplified input signal responsive to the isolation control signal.

4. The integrated receiver of claim 1 wherein the isolation control signal generator comprises a one-shot circuit configured to generate an output pulse of a predetermined duration responsive to a falling edge in the delayed digital output signal.

5. The integrated receiver of claim 1 wherein the isolation control signal generator comprises an edge triggered one-shot circuit configured to generate an output pulse of a predetermined duration responsive to each edge in the delayed digital output signal.

6. The integrated receiver of claim 5 wherein the edge triggered one-shot circuit comprises:

a first exclusive-OR gate having first and second input terminals and an output terminal, wherein the first input terminal is configured to receive the delayed digital output signal;

a resistor having first and second terminals, wherein the first terminal is configured to receive the delayed digital output signal, and further wherein the second terminal is coupled to the second input terminal of the first exclusive-OR gate; and

a capacitor coupled between the second input terminal of the first exclusive-OR gate and ground;

whereby the first exclusive-OR gate generates the isolation control signal at its output terminal responsive to the delayed digital output signal.

7. The integrated receiver of claim 5 wherein the isolation control signal generator further includes:

a feedback detect comparator configured to receive the amplified input signal and compare it to the detection threshold voltage level to produce a feedback detect signal;

a second exclusive-OR gate having first and second input terminals and an output terminal, wherein the first input terminal is configured to receive the feedback detect signal and the second input terminal is configured to receive the delayed digital output signal; and

an AND gate having first and second input terminals and an output terminal, wherein the first input terminal is coupled to the output terminal of the first exclusive-OR gate and the second input terminal is coupled to the output terminal of the second exclusive-OR gate whereby the AND gate generates the isolation control signal at its output terminal.

8. An infrared receiver circuit formed on a substrate, the circuit comprising:

a first diffusion in the substrate;

an input amplifier having first and second input terminals, a gain control terminal and an output terminal, the first input terminal being configured to receive a first bias voltage and the second input terminal being coupled to the first diffusion;

a bandpass filter having input and output terminals, the input terminal being coupled to the output terminal of the input amplifier;

a comparator having first and second input terminals and an output terminal, the first input terminal being configured to receive a detection threshold voltage, the second input terminal being coupled to the output of the bandpass filter, and the output terminal being coupled to an output terminal of the receiver circuit;

an automatic gain control circuit having first and second input terminals and an output terminal, the first input terminal being coupled to the output of the bandpass filter, the second input terminal being configured to receive an automatic gain control threshold voltage, and the output terminal being coupled to the gain control terminal of the input amplifier;

a delay circuit having input and output terminals, wherein the input terminal is coupled to the output terminal of the comparator such that a delayed digital output signal is generated at the output terminal of the delay circuit responsive to an input data signal received at the input terminal of the delay circuit;

an isolation control signal generator having input and output terminals, wherein the input terminal is coupled to the output terminal of the delay circuit, and wherein the isolation control signal generator is configured to generate a pulse of predetermined duration at its output terminal responsive to an edge in the delayed digital output signal; and

an isolation switch having input, output and control terminals, the control terminal being coupled to the output terminal of the isolation control signal generator such that the isolation switch isolates the input terminal thereof from the output terminal thereof responsive to the automatic gain control signal, the input terminal of the isolation switch being coupled to the output terminal of the input amplifier, the output terminal of the isolation switch being coupled to the first input terminal of the automatic gain control circuit such that the isolation switch is interposed between the first input terminal of the automatic gain control circuit and the output terminal of the input amplifier whereby the isolation switch isolates the automatic gain control circuit from the output terminal of the input amplifier responsive to the isolation control signal.

9. The receiver of claim 8 wherein the output terminal of the isolation switch is further coupled to the second input terminal of the comparator such that the isolation switch is interposed between the second input terminal of the comparator and the output terminal of the input amplifier whereby the isolation switch isolates the comparator from the output terminal of the input amplifier responsive to the isolation control signal.

10. The receiver of claim 8 wherein the output terminal of the isolation switch is further coupled to the input terminal of the bandpass filter such that the isolation switch is interposed between the input terminal of the bandpass filter and the output terminal of the input amplifier whereby the isolation switch isolates the bandpass filter from the output terminal of the input amplifier responsive to the isolation control signal.

11. The receiver of claim 9 wherein the output terminal of the isolation switch is further coupled to the input terminal of the bandpass filter such that the isolation switch is interposed between the input terminal of the bandpass filter and the output terminal of the input amplifier whereby the isolation switch isolates the bandpass filter from the output terminal of the input amplifier responsive to the isolation control signal.

12. The receiver of claim 11 wherein the isolation control signal generator comprises a one-shot circuit configured to generate an output pulse of a predetermined duration at the output terminal responsive to a falling edge in the delayed digital output signal.

13. The receiver of claim 11 wherein the isolation control signal generator comprises an edge triggered one-shot circuit configured to generate an output pulse of a predetermined duration at the output terminal responsive to each edge in the delayed digital output signal.

14. The receiver of claim 13 wherein the edge triggered one-shot circuit comprises:

a first exclusive-OR gate having first and second input terminals and an output terminal, the first input terminal being coupled to the output terminal of the delay circuit and the output terminal being coupled to the control terminal of the isolation switch;

a resistor having first and second terminals, the first terminal being coupled to the output terminal of the delay circuit, and the second terminal being coupled to the second input terminal of the first exclusive-OR gate; and

a capacitor coupled between the second input terminal of the first exclusive-OR gate and ground;

whereby the first exclusive-OR gate generates the isolation control signal at its output terminal responsive to the delayed digital output signal.

15. The receiver of claim 14 wherein the isolation control signal generator further includes:

a feedback detect comparator having first and second input terminals and an output terminal, the first input terminal being coupled to the output terminal of the input amplifier, and the second input terminal being configured to receive the detection threshold voltage;

a second exclusive-OR gate having first and second input terminals and an output terminal, the first input terminal being coupled to the output terminal of the feedback detect comparator, and the second input terminal being coupled to the output terminal of the delay circuit; and

an AND gate having first and second input terminals and an output terminal, the first input terminal being coupled to the output terminal of the first exclusive-OR gate, the second input terminal being coupled to the output terminal of the second exclusive-OR gate, and the output terminal being coupled to the control terminal of the isolation switch.

16. The infrared receiver circuit of claim 8, the circuit further comprising:

a second diffusion in the substrate;

an opaque shield formed over the second diffusion and spaced apart from the first diffusion; and

wherein the second diffusion is coupled to the first input terminal of the input amplifier.

17. A method for suppressing feedback in a photodiode and a receiver fabricated on a substrate, the method comprising the steps:

receiving an input signal with the photodiode;

amplifying the input signal to produce an amplified input signal;

controlling the gain of the input signal amplification responsive to the magnitude of the amplified input signal;

comparing the amplified input signal to a detection threshold voltage to produce a digital output signal; and

holding the gain at a substantially constant level in response to a fast signal transition in the digital output signal.

18. The method of claim 17 including the step of filtering the amplified input signal to produce a filtered input signal.

19. The method of claim 17 wherein:

the step of controlling the gain of the input signal amplification responsive to the magnitude of the amplified input signal includes the step of controlling the gain using an automatic gain control circuit; and

the step of holding the gain at a substantially constant level includes the steps;

generating an isolation signal responsive to the digital output signal, and

isolating the automatic gain control circuit from the amplified input signal responsive to the isolation signal.

20. The method of claim 19 wherein the step of comparing the amplified input signal to a detection threshold voltage includes using a comparator circuit to compare the amplified input signal to the detection threshold voltage and further including the step of isolating the comparator from the amplified input signal responsive to the isolation signal.

21. The method of claim 19 including:

filtering the amplified input signal using a bandpass filter to produce a filtered input signal; and

isolating the bandpass filter from the amplified input data signal responsive to the isolation signal.

22. The method of claim 19 wherein the step of generating an isolation signal includes generating a pulse of a predetermined duration responsive to each falling edge in the digital output signal.

23. The method of claim 19 wherein the step of generating an isolation signal includes generating a pulse of a predetermined duration responsive to each edge in the digital output signal.

24. The method of claim 17 wherein the step of comparing the filtered input signal to a detection threshold voltage to produce a digital output signal includes the step of introducing a time delay to the digital output signal.