Electronic package having flip chip integrated circuit and passive chip component

• US 6,356,453 B1
• Filed: 06/29/2000
• Issued: 03/12/2002
• Est. Priority Date: 06/29/2000
• Status: Expired due to Term

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Scanlan, Christopher, Juskey, Frank, OʼBrien, Pat
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): Vigushin, John B.
• Application Number:
  US09/608,678
• Time in Patent Office: 621 Days
• Field of Search: 361/760, 361/782, 361/783, 361/784, 257/700, 257/723, 257/724, 257/728, 257/737, 257/738, 257/778, 257/787, 298/40, 298/41, 228/180.21, 228/180.22, 438/108, 438/126, 438/127
• US Class Current: 361/760
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H05K 3/284 : for encapsulating mounted components H05K1/185 takes precedence
• CPC Class Codes: H05K 3/3463 : Solder compositions in relation to features of the printed circuit board or the mounting process

Abstract

A package includes both a flip chip mounted active Chip component and a passive chip component. The flip chip bumps between the bond pads of the active chip component and the substrate are low impedance. Further, by mounting the active chip component as a flip chip, the area on the substrate occupied by the active chip component is approximately equal to the area of the active chip component.

Claims

1. A package comprising:

a substrate having a first surface having a first trace and a second trace formed thereon;

a passive chip component having a first terminal;

a solder joint electrically connecting said first terminal to said first trace, said solder joint comprising a first solder;

an active chip component having a first surface with a bond pad formed thereon; and

a bump electrically connecting said bond pad to said second trace, said bump comprising a second solder having a lower melting temperature than said first solder.

2. The package of claim 1 wherein said active chip component is mounted as a flip chip.

3. The package of claim 1 further comprising an underfill material enclosing said bump and filling a region between said first surface of said active chip component and said first surface of said substrate.

4. The package of claim 3 wherein said underfill material contacts sides of said active chip component.

5. The package of claim 4 wherein said underfill material contacts a second surface of said active chip component opposite said first surface of said active chip component.

6. The package of claim 1 wherein said passive chip component is selected from the group consisting of a resistor, capacitor, and inductor.

7. The package of claim 1 wherein said active chip component is an integrated circuit.

8. The package of claim 7 wherein said active chip component is a radio frequency (RF) integrated circuit.

9. The package of claim 1 further comprising a first contact on said first trace, said solder joint being physically and electrically connected to said first contact.

10. The package of claim 1 further comprising a first contact on said second trace, said bump being physically and electrically connected to said first contact.

11. The package of claim 1 further comprising an array type substrate including a plurality of individual substrates integrally connected together in an array format, said plurality of individual substrates comprising said substrate.

12. A package comprising:

a substrate having a first surface having a passive chip component trace and an active chip component trace formed thereon;

a passive chip component having a surface with a first terminal formed thereon;

a first contact on said passive chip component trace;

a solder joint electrically connecting said first terminal to said first contact, said solder joint comprising a first solder;

an active chip component having a first surface with a bond pad formed thereon;

a second contact on said active chip component trace; and

a bump electrically connecting said bond pad to said second contact such that said active chip component is mounted as a flip chip, said bump comprising a second solder having a lower melting temperature than said first solder.

13. A package comprising:

a substrate having a first surface having a first trace and a second trace formed thereon;

a passive chip component having a first terminal;

a solder joint electrically connecting said first terminal to said first trace;

an active chip component having a first surface with a bond pad formed thereon;

a bump electrically connecting said bond pad to said second trace;

an underfill material enclosing said bump and filling a region between said first surface of said active chip component and said first surface of said substrate; and

a layer of encapsulant enclosing said active chip component, said passive chip component, said underfill material, and said solder joint.

14. The package of claim 13 wherein said bump is selected from the group consisting of solder, gold, electrically conductive epoxy paste, and electrically conductive epoxy film.

15. The package of claim 13 wherein said layer of encapsulant has a smooth exposed first surface.