Flash based control for field programmable gate array
First Claim
Patent Images
1. A circuit for controlling a switching transistor comprising:
- a control gate potential node;
an output node;
a p-channel floating gate flash memory transistor having a drain electrically coupled to a first voltage potential, a floating gate, a control gate coupled to said control gate potential node, and a source coupled to said output node;
an n-channel floating gate flash memory transistor having a drain electrically coupled to said output node, a floating gate, a control gate coupled to said control gate potential node, and a source coupled to a second voltage potential;
wherein said floating gate of said p-channel floating gate flash memory transistor is electrically coupled to said floating gate of said n-channel floating gate memory transistor; and
wherein said output node is coupled to said switching transistor.
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Abstract
A circuit for controlling a switching transistor in a reprogrammable FPGA device comprises first and second floating gate flash memory transistors. A first floating gate flash memory transistor has a drain electrically coupled to a first voltage potential, a floating gate, a control gate coupled to a control gate node, and a source coupled to an output node. A second floating gate flash memory transistor has a drain electrically coupled to the output node, a floating gate, a control gate coupled to the control gate node, and a source coupled to a second voltage potential. The output node is coupled to the gate of a switching transistor.
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Citations
6 Claims
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1. A circuit for controlling a switching transistor comprising:
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a control gate potential node;
an output node;
a p-channel floating gate flash memory transistor having a drain electrically coupled to a first voltage potential, a floating gate, a control gate coupled to said control gate potential node, and a source coupled to said output node;
an n-channel floating gate flash memory transistor having a drain electrically coupled to said output node, a floating gate, a control gate coupled to said control gate potential node, and a source coupled to a second voltage potential;
wherein said floating gate of said p-channel floating gate flash memory transistor is electrically coupled to said floating gate of said n-channel floating gate memory transistor; and
wherein said output node is coupled to said switching transistor.
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2. A circuit for controlling a switching transistor comprising:
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a control gate potential node;
an output node;
a p-channel floating gate flash memory transistor having a drain electrically coupled to a first voltage potential, a floating gate, a control gate coupled to said control gate potential node, and a source coupled to said output node;
an n-channel floating gate flash memory transistor having a drain electrically coupled to said output node, a floating gate, a control gate coupled to said control gate potential node, and a source coupled to a second voltage potential;
wherein said floating gate of said p-channel floating gate flash memory transistor and said floating gate of said n-channel floating gate memory transistor are formed from a single contiguous piece of polysilicon; and
wherein said output node is coupled to said switching transistor. - View Dependent Claims (3, 5, 6)
said first and second voltage potentials are independently switchable between programming potentials and an operating potentials; and
said control gate potential node is switchable between a programming potential and an operating potential.
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5. The method of claim 3 wherein:
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programming said floating gate such that said first floating gate flash memory transistor is turned on if said switching transistor is to be turned on; and
programming said floating gate such that said second floating gate flash memory transistor is on if said switching transistor is to be turned off.
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6. The method of claim 3 wherein:
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programming said first floating gate flash memory transistor and second gate flash memory transistor comprises applying a programming potential between said control gate potential node and the drain of said first floating gate memory transistor;
programming said second floating gate flash memory transistor comprises applying said programming potential between said control gate potential node and the source of said second gate flash memory transistor.
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4. A method for controlling a switching transistor comprising:
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providing said switching transistor having a gate;
providing a first floating gate flash memory transistor having a drain electrically coupled to a first voltage potential, a floating gate, a control gate coupled to a control gate potential node, and a source coupled to an output node;
providing a second floating gate flash memory transmitter having drain electrically coupled to said output node, a floating gate, a control gate coupled to said control gate potential node, and a source coupled to a second voltage potential;
providing a single contiguous piece of polysilicon forming said floating gate of said first floating gate flash memory transistor and said floating gate of said second floating gate flash memory transistor;
coupling said output node to said switching transistor;
programming said floating gate to a first state if said switching transistor is to be turned on; and
programming said floating gate to a second state if said switching transistor is to be turned off.
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Specification