Merging write cycles by comparing at least a portion of the respective write cycle addresses

• US 6,356,485 B1
• Filed: 02/12/2000
• Issued: 03/12/2002
• Est. Priority Date: 02/13/1999
• Status: Expired due to Term

• Current Assignee: InnoMemory, LLC (Jeffrey M. Gross)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Proebsting, Robert J.
• Primary Examiner(s): Le, Vu A.
• Assistant Examiner(s): Nguyen, Tuan T.
• Application Number:
  US09/503,048
• Time in Patent Office: 759 Days
• Field of Search: 365/189.01, 365/189.07, 365/222
• US Class Current: 365/189.16
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 2207/229 Timing of a write operation
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H10B 12/488 Word lines
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A high performance dynamic memory array architecture is disclosed in several embodiments, along with various embodiments of associated supporting circuitry. An exemplary 18 MBit memory array integrated circuit includes four banks of arrays and a write queue for storing at least one pending write cycle. At least a portion of the address information associated with a pending internal write operation is compared to corresponding address information associated with a subsequently-received write cycle request to determine whether a first group of memory cells to be otherwise written by the pending internal write operation and a second group of memory cells to be otherwise written by another internal write operation corresponding to a subsequently-received write cycle request may instead be both written using a single internal write operation. If so, then the pending internal write operation is skipped, the write data associated with the subsequently-received write cycle request is merged into, and supersedes any commonly-addressed data bits of, the write data associated with the pending internal write operation, and a single internal write operation is performed to write the merged data. Alternatively, if the first and second groups of memory cells cannot be written using a single internal write operation, the pending internal write operation is performed in its normal order, and then another internal write operation is performed to write data associated with the subsequently-received write cycle request.

Claims

1. An integrated circuit comprising:

a memory array including a plurality of memory cells;

a write queue circuit for storing address information and data for at least one pending internal write operation into the memory array;

a write decision circuit for determining whether a first group of memory cells to be otherwise written by a pending internal write operation stored within the write queue circuit, and a second group of memory cells to be otherwise written by another internal write operation corresponding to a subsequently-received write cycle request, may instead be both written using a single internal write operation;

a write data merging circuit responsive to the write decision circuit for merging, if the first and second groups of memory cells may be both written using a single internal write operation, write data associated with the subsequently-received write cycle request into, and superseding any commonly-addressed data bits of, write data associated with the pending internal write operation; and

an internal write operation control circuit configured to perform a single internal write operation to write the merged data into the memory array if the first and second groups of memory cells may both be written using a single internal write operation.

2. An integrated circuit as in claim 1 wherein:

the internal write operation control circuit is further arranged, if the first and second groups of memory cells may both be written using a single internal write operation, to omit the pending internal write operation, and to perform the single internal write operation to write the merged data into the memory array at a time after the pending internal write operation would otherwise have been performed.

3. An integrated circuit as in claim 1 wherein:

the internal write operation control circuit is further arranged, if the first and second groups of memory cells may both be written using a single internal write operation, to perform the single internal write operation to write the merged data into the memory array at a time when the pending internal write operation would otherwise have been performed, and to omit an internal write operation that would have subsequently been performed corresponding to the subsequently-received write cycle request.

4. An integrated circuit as in claim 1 wherein:

the write decision circuit is arranged to compare at least a portion of the address information associated with the pending internal write operation to corresponding address information associated with the subsequently-received write cycle request.

5. An integrated circuit as in claim 4 wherein:

the subsequently-received write cycle request includes internally generated address information for a subsequent write cycle of a burst.

6. An integrated circuit as in claim 4 wherein:

the subsequently-received write cycle request includes an externally-received address.

7. An integrated circuit as in claim 4 wherein:

the address information for a given write cycle request comprises a non-decoded address.

8. An integrated circuit as in claim 4 wherein:

the address information for a given write cycle request comprises a partially decoded address.

9. An integrated circuit as in claim 1 wherein:

the write decision circuit is arranged to determine whether the first and second groups of memory cells may be both written using a single internal write operation by utilizing a signal indicating that the subsequently-received write cycle request corresponds to a subsequent write cycle of a burst.

10. An integrated circuit as in claim 1 wherein:

power consumed by the integrated circuit is reduced by performing a single internal write operation to write the merged data.

11. An integrated circuit as in claim 2 wherein:

the memory array comprises a dynamic memory array; and

the internal write operation control circuit is arranged to make available for an internal refresh cycle a time when the pending internal write operation, if omitted, would otherwise have been performed.

12. An integrated circuit as in claim 11 further comprising a refresh control circuit configured to perform an internal refresh cycle, if one is pending, during the time when the pending internal write operation, if omitted, would otherwise have been performed, thereby sneaking in a refresh cycle at a time when the memory array would not otherwise have been available for a refresh cycle.

13. An integrated circuit as in claim 1 wherein the memory array comprises a static memory array.

14. An integrated circuit as in claim 1 further comprising a processor arranged to interact with the memory array.

15. An integrated circuit as in claim 1 wherein the integrated circuit includes:

a data receiving circuit for receiving data associated with a write cycle request and communicated to the integrated circuit on an external data bus; and

an internal data bus for writing data into the memory array having a bus width that is N times wider than the external data bus, where N is a positive integer greater than 1.

16. An integrated circuit as in claim 15 wherein the external data bus is a bi-directional data bus.

17. An integrated circuit as in claim 15 wherein:

the internal data bus for writing data into the memory array includes independently enabled portions thereof so that, for any given internal write operation, any number of the portions may be independently enabled to simultaneously write data associated with the respective portion into the memory array, with remaining portions disabled to prevent any data associated therewith to be written into the memory array.

18. An integrated circuit as in claim 17 wherein the independently enabled portions of the internal data bus are of a size such that one or more of the portions may be enabled to simultaneously write into the memory array a data word equal in size to that of the external data bus.

19. An integrated circuit as in claim 18 wherein all of the portions may be enabled to simultaneously write into the memory array N data words, each equal in size to that of the external data bus.

20. An integrated circuit as in claim 18 wherein the independently enabled portions of the internal data bus are each equal in size to that of an external data word communicated on the external data bus.

21. An integrated circuit as in claim 18 wherein the independently enabled portions of the internal data bus are each equal in size to that of a byte within an external data word communicated on the external data bus.

22. An integrated circuit as in claim 19 wherein:

the N data words correspond respectively to N external data words communicated on the external data bus having respective addresses which differ only in the least significant log₂N bits.

23. An integrated circuit as in claim 22 wherein:

N equals 2; and

the two data words correspond respectively to two external data words having respective addresses which differ only in the least significant bit, thereby providing that pairs of sequentially addressed consecutive write cycle requests may be merged and carried out as single internal write operations.

24. An integrated circuit as in claim 23 wherein:

each external data word comprises four 8-bit bytes of data.

25. An integrated circuit as in claim 24 wherein:

each external data word comprises four 9-bit bytes of data.

26. An integrated circuit as in claim 22 wherein:

N equals 4; and

the four data words correspond respectively to four external data words having respective addresses which differ only in the two least significant bits, thereby providing that quads of sequentially addressed consecutive write cycle requests may be merged and carried out as single internal write operations.

27. An integrated circuit as in claim 15 further comprising:

an address receiving circuit for receiving an address, communicated to the integrated circuit on an external address bus, associated with a write cycle request.

28. An integrated circuit as in claim 27 wherein:

the address receiving circuit is configured to receive the address associated with a given write cycle request at a particular time; and

the data receiving circuit is configured to receive the data associated with the given write cycle request at a time other than the particular time.

29. An integrated circuit as in claim 27 wherein:

the address receiving circuit is configured to receive the address associated with a given write cycle request at a particular time; and

the data receiving circuit is configured to receive the data associated with the given write cycle request at substantially the particular time.

30. An integrated circuit as in claim 1 wherein the integrated circuit further comprises:

a data receiving circuit for receiving data associated with a write cycle request and communicated to the integrated circuit on an external data bus; and

an internal data bus for writing data into the memory array having a bus width that is at least as wide as the external data bus, and having independently enabled portions of the internal data bus so that, for any given internal write operation, any number of the portions may be independently enabled to simultaneously write data associated with each respective enabled portion into the memory array, and to prevent any data associated with remaining portions from being written into the memory array.

31. An integrated circuit as in claim 30 wherein the independently enabled portions of the internal data bus are each equal in size to a byte within an external data word communicated on the external data bus.

32. An integrated circuit as in claim 31 wherein:

consecutive write cycle requests, each writing one or more bytes to a particular addressed word, may be merged and carried out as a single internal write operation.

33. An integrated circuit as in claim 1 wherein the write queue circuit comprises:

a plurality of entries for storing both address information and data associated with a corresponding plurality of pending internal write operations corresponding to write cycle requests received by the integrated circuit and not yet written into the memory array.

34. An integrated circuit as in claim 33 wherein:

the oldest entry in the write queue circuit is implemented using a single localized storage register for storing address information and data to be written into the memory array corresponding to the oldest pending internal write operation.

35. An integrated circuit as in claim 34 wherein:

the oldest entry in the write queue circuit is located in close proximity to the remaining entries in the write queue circuit.

36. An integrated circuit as in claim 33 wherein:

the oldest entry in the write queue circuit is implemented using a plurality of storage registers each associated with a respective portion of the memory array, for storing address information and data to be written into the respective portion of the memory array, if any, corresponding to the oldest pending internal write operation.

37. An integrated circuit as in claim 36 wherein:

the plurality of storage registers are physically distributed within the integrated circuit, with each respective register located near the respective portion of the memory array.

38. An integrated circuit as in claim 1 further comprising:

a read bypass circuit for supplying write data stored within the write queue circuit and not yet written into the memory array, when carrying out a subsequently-received read cycle request received by the integrated circuit which addresses memory cells to be written with the write data stored within the write queue circuit.

39. An integrated circuit as in claim 38 wherein the read bypass circuit comprises:

a read decision circuit for comparing at least a portion of the address information associated with a pending internal write operation stored within the write queue circuit to corresponding address information associated with a subsequently-received external read cycle request, and for determining whether the subsequently-received read cycle request addresses any memory cells to be written by the pending internal write operation; and

a read data bypass circuit responsive to the read decision circuit for merging write data associated with the pending internal write operation stored within the write queue circuit and not yet written into the memory array into, and superseding any commonly-addressed data bits of, any read data retrieved from the memory array when carrying out the subsequently-received external read cycle request.

40. An integrated circuit as in claim 39 wherein:

the read bypass circuit is arranged so that write data associated with a given pending internal write operation stored within the write queue circuit takes precedence over any commonly-addressed data bits of write data associated with older pending internal write operations stored within the write circuit when merging write data into read data retrieved from the memory array.

41. An integrated circuit as in claim 36 further comprising:

a read bypass circuit for supplying write data stored within the write queue circuit and not yet written into the memory array, when carrying out a subsequently-received read cycle request received by the integrated circuit which addresses memory cells to be written with the write data stored within the write queue circuit;

wherein the oldest entry in the write queue circuit is also implemented using another storage register for storing address information and data to be written into the memory array, said another register being located in close proximity to the remaining entries in the write queue circuit; and

wherein the read data bypass circuit is arranged to use address information and data from said another storage register to facilitate merging of data with other entries within the write queue circuit.

42. An integrated circuit as in claim 33 wherein:

the write decision circuit is arranged to compare at least a portion of the address information associated with the oldest pending internal write operation stored within the write queue circuit to corresponding address information associated with the next oldest pending internal write operation stored within the write queue circuit; and

the write data merging circuit is arranged to merge write data corresponding to the oldest pending internal write operation with, and superseded by any commonly-addressed data bits of, the data associated with the next oldest pending internal write operation.

43. An integrated circuit comprising:

a memory array including a plurality of memory cells;

write queue means for storing at least address information for at least one pending internal write operation;

means for determining whether a first group of memory cells to be otherwise written by a pending internal write operation and a second group of memory cells to be otherwise written by another internal write operation corresponding to a subsequently-received write cycle request may instead be both written using a single internal write operation;

means for merging write data associated with the subsequently-received write cycle request into, and superseding any commonly-addressed data bits of, write data associated with the pending internal write operation; and

means for performing a single internal write operation to write the merged data rather than two separate internal write operations.

44. An integrated circuit as in claim 43 further comprising:

an external data bus for receiving data associated with a write cycle request; and

an internal data bus for writing data into the memory array having a bus width that is N times wider than the external data bus, where N is a positive integer greater than 1.

45. In an integrated circuit having a memory array and containing a write queue for storing at least address information associated with at least one pending internal write operation into the memory array, a method of operating the integrated circuit comprising:

determining whether a first group of memory cells to be otherwise written by a pending internal write operation and a second group of memory cells to be otherwise written by another internal write operation corresponding to a subsequently-received write cycle request may instead be both written using a single internal write operation; and

if so, then

merging write data associated with the subsequently-received write cycle request into, and superseding any commonly-addressed data bits of, write data associated with the pending internal write operation; and

performing a single internal write operation to write the merged data into the memory array.

46. A method as in claim 45 wherein:

the subsequently-received write cycle request comprises the next write cycle request after an earlier write cycle request that gave rise to the pending internal write operation.

47. A method as in claim 46 wherein:

at least one non-write cycle request is received after the earlier write cycle request that gave rise to the pending internal write operation and before the next write cycle request.

48. A method as in claim 45 wherein:

the subsequently-received write cycle request comprises a write cycle request other than the next write cycle request after an earlier write cycle request that gave rise to the pending internal write operation.

49. A method as in claim 45 wherein:

the write queue is arranged to store at least address information associated with the pending internal write operation and at least one additional write cycle request;

the subsequently-received write cycle request is also stored within the write queue along with the pending internal write operation when the determining step is performed.

50. A method as in claim 45 wherein:

the subsequently-received write cycle request is not stored within the write queue when the determining step is performed.

51. A method as in claim 45 wherein the determining step comprises:

comparing at least a portion of the address of the pending internal write operation to the corresponding address portion of the subsequently-received write cycle request.

52. A method as in claim 45 wherein the determining step comprises:

acting on a signal indicating the subsequently-received write cycle request corresponds to a subsequent write cycle of a burst.

53. A method as in claim 45 wherein the integrated circuit includes:

an external data bus for conveying data associated with a write cycle request; and

an internal data bus for writing data into the memory array having a bus width that is N times wider than the external data bus, where N is a positive integer greater than 1.

54. A method as in claim 45 further comprising:

determining whether the first and second groups of memory cells to be otherwise written by an internal write operation to write the merged data, and a third group of memory cells to be otherwise written by yet another internal write operation corresponding to a write cycle request following the subsequently-received write cycle request, may instead be written using a single internal write operation; and

if so, then

merging write data corresponding to the write cycle request following the subsequently-received write cycle request into, and superseding any commonly-addressed data bits of, the previously merged data; and

performing a single internal write operation to write the newly merged data.

55. In an integrated circuit having a memory array and containing a write queue for storing at least address information associated with at least one pending internal write operation into the memory array, a method of operating the integrated circuit comprising:

comparing at least a portion of the address information associated with a pending internal write operation stored within the write queue to corresponding address information associated with a subsequently-received write cycle request to determine whether a first group of memory cells to be otherwise written by the pending internal write operation and a second group of memory cells to be otherwise written by another internal write operation corresponding to a subsequently-received write cycle request may instead be both written using a single internal write operation;

if so, then

skipping the pending internal write operation;

merging write data associated with the subsequently-received write cycle request into, and superseding any commonly-addressed data bits of, write data associated with the pending internal write operation; and

performing a single internal write operation to write the merged data;

if not so, then

performing the pending internal write operation in its normal order; and

then

performing another internal write operation to write data associated with the subsequently-received write cycle request.

56. A method as in claim 55 wherein:

power consumed by the integrated circuit is reduced by skipping the pending internal write operation and performing a single internal write operation to write the merged data.

57. A method as in claim 55:

wherein the memory array comprises a dynamic memory array.

58. A method as in claim 57 further comprising:

performing an internal refresh cycle, if one is pending, during the time when the pending internal write operation, if skipped, would otherwise have been performed, thereby sneaking in a refresh cycle at a time when the memory array would not otherwise have been available for a refresh cycle.

59. A method as in claim 55 wherein the memory array comprises a static memory array.

60. A method as in claim 55 further comprising:

receiving data associated with a write cycle request and communicated to the integrated circuit on an external data bus;

writing data into the memory array when performing an internal memory operation using an internal data bus having a bus width that is N times wider than the external data bus, where N is a positive integer greater than 1.

61. A method as in claim 60 further comprising:

independently enabling any number of portions of the internal data bus, for a given internal write operation, to simultaneously write data associated with each enabled portion into the memory array; and

disabling remaining portions of the internal data bus, for the given internal write operation, to prevent any data associated therewith to be written into the memory array.

62. A method as in claim 61 wherein the independently enabled portions of the internal data bus are of a size such that one or more of the portions may be enabled to simultaneously write into the memory array a data word equal in size to that of an external data word communicated on the external data bus.

63. A method as in claim 62 wherein all of the portions may be enabled to simultaneously write into the memory array N data words, each equal in size to that of an external data word communicated on the external data bus.

64. A method as in claim 62 wherein the independently enabled portions of the internal data bus are each equal in size to that of an external data word communicated on the external data bus.

65. A method as in claim 62 wherein the independently enabled portions of the internal data bus are each equal in size to that of a byte within an external data word communicated on the external data bus.

66. A method as in claim 63 wherein the N data words correspond respectively to N external data words communicated on the external data bus having respective addresses which differ only in the least significant log₂N bits.

67. A method as in claim 66 wherein:

N equals 2;

the two data words correspond respectively to two external data words having respective addresses which differ only in the least significant bit, thereby providing that pairs of sequentially addressed consecutive write cycle requests may be merged and carried out as single internal write operations.

68. A method as in claim 67 wherein:

each external data word comprises four 8-bit bytes of data.

69. A method as in claim 67 wherein:

each external data word comprises four 9-bit bytes of data.

70. A method as in claim 60 further comprising:

receiving an address associated with a given write cycle request at a particular time; and

receiving the data associated with the given write cycle request at a time other than the particular time.

71. A method as in claim 60 further comprising:

receiving an address associated with a given write cycle request at a particular time; and

receiving the data associated with the given write cycle request at substantially the particular time.