Reduced power DRAM device and method
First Claim
Patent Images
1. A memory device comprising:
- a plurality of memory sub arrays;
a power distribution terminal coupled to said plurality of memory sub arrays, said power distribution terminal selectively providing power to said plurality of memory sub arrays; and
internal memory control logic coupled to said power distribution terminal, said internal memory control logic receiving a memory command and data which identifies a range of addresses required for said memory command and identifying which ones of said plurality of memory sub arrays contain said addresses within said range, said internal memory control logic causing said power distribution terminal to supply power only to said plurality of memory sub arrays containing said addresses in said range.
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Abstract
A memory device and method employing a scheme for reduced power consumption is disclosed. By dividing a memory array sector into memory sub arrays, the memory device can provide power to memory sub arrays that need to be powered up or, in the alternative, powered down. This reduces the power consumption and heat generation associated with high speed and high capacity memory devices.
176 Citations
39 Claims
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1. A memory device comprising:
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a plurality of memory sub arrays;
a power distribution terminal coupled to said plurality of memory sub arrays, said power distribution terminal selectively providing power to said plurality of memory sub arrays; and
internal memory control logic coupled to said power distribution terminal, said internal memory control logic receiving a memory command and data which identifies a range of addresses required for said memory command and identifying which ones of said plurality of memory sub arrays contain said addresses within said range, said internal memory control logic causing said power distribution terminal to supply power only to said plurality of memory sub arrays containing said addresses in said range. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory module comprising:
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at least one memory chip, said at least one memory chip comprising;
a plurality of memory sub arrays;
a power distribution terminal coupled to said plurality of memory sub arrays, said power distribution terminal selectively providing power to said plurality of memory sub arrays; and
internal memory control logic coupled to said power distribution terminal, said internal memory control logic receiving a memory command and data which identifies a range of addresses required for said memory command and identifying which ones of said plurality of memory sub arrays contain said addresses within said range, said internal memory control logic causing said power distribution terminal to supply power only to said plurality of memory sub arrays containing said addresses in said range. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A processor system comprising:
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a processor; and
a memory device coupled to said processor, said memory device comprising;
a plurality of memory sub arrays;
a power distribution terminal coupled to said plurality of memory sub arrays, said power distribution terminal selectively providing power to said plurality of memory sub arrays; and
internal memory control logic coupled to said power distribution terminal, said internal memory control logic receiving a memory command and data which identifies a range of addresses required for said memory command and identifying which ones of said plurality of memory sub arrays contain said addresses within said range, said internal memory control logic causing said power distribution terminal to supply power only to said plurality of memory sub arrays containing said addresses in said range. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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25. A method of operating a memory device, said method comprising:
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receiving a memory command and data which identifies a range of addresses required for said memory command within a memory device;
identifying which of a plurality of memory sub arrays contains said addresses within said range; and
supplying power to said identified memory sub arrays which contains said addresses within said range. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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Specification