Field programmable gate arrays

• US 6,356,637 B1
• Filed: 09/18/1998
• Issued: 03/12/2002
• Est. Priority Date: 09/18/1998
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Garnett, Paul Jeffrey
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Callahan, Paul E.
• Application Number:
  US09/157,205
• Time in Patent Office: 1,271 Days
• Field of Search: 380/44, 380/45, 380/46, 380/265, 380/28, 713/193, 713/194, 713/200
• US Class Current: 380/265
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A volatile field programmable gate array (FPGA) having a configurable logical structure portion that is configurable with encrypted configuration data stored external to the FPGA in configuration data memory. On FPGA reconfiguration, for example on power-up, the encrypted configuration data is supplied to an input of the FPGA. In the FPGA, the configuration data is first decrypted by a decryption algorithm embedded in logic, the algorithm using as an operand a decryption key stored in the FPGA in a non-volatile memory, for example EEPROM. The decrypted configuration data is then distributed to the volatile functional portion of the FPGA in a conventional manner. The functional portion may be SRAM. With this design, unauthorized reading of the configuration data of the FPGA by observation of the stream of configuration data transmitted to the FPGA from the external memory, for example during power-up, will only result in encrypted configuration data being obtained. In this way, the design affords enhanced security against the loss of commercially valuable intellectual property and confidential information constituted by the unencrypted configuration data.

Claims

1. A field programmable gate array comprising:

input for receiving encrypted configuration data;

a configurable logical structure having a default state and being programmable into any one of a plurality of programmed states, each defined by a set of decrypted configuration data; and

data storage for storing a set of decrypted configuration data for defining one of the programmed states,

wherein, in the default state, the configurable logic structure is configured to decrypt encrypted configuration data received at the input and to store a corresponding decrypted configuration data set in the data storage for subsequent reconfiguration of the configurable logic structure into the programmed state defined by that decrypted configuration data set.

2. A field programmable gate array according to claim 1, wherein the data storage comprises a plurality of configuration data holding registers.

3. A field programmable gate array according to claim 1, comprising a state machine connected to detect completion of decryption by the configurable logic structure and to trigger the data storage to load the configuration data stored therein into the configurable logic structure, thereby to reconfigure the configurable logic structure into a programmed state.

4. A field programmable gate array according to claim 1, wherein the configurable logical structure is formed of volatile elements.

5. A field programmable gate array according to claim 4 wherein the volatile elements are SRAM elements.

6. A field programmable gate array according to claim 1, further comprising a key input through which a decryption key is loadable a decryption key storage.

7. A field programmable gate array according to claim 6, further comprising a disabling element constructed so that receipt of an externally applicable disabling signal causes an irreversible change to the field programmable gate array so as to bar subsequent external communication to the decryption key storage.