Method and apparatus for controlling operations in a vehicle

• US 6,356,813 B1
• Filed: 10/11/2000
• Issued: 03/12/2002
• Est. Priority Date: 10/11/1999
• Status: Expired due to Fees

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Sommer, Rainer, Gieseler, Steffen, Ege, Taskin
• Primary Examiner(s): Cuchlinski, Jr., William A.
• Assistant Examiner(s): TO, TUAN C
• Application Number:
  US09/686,674
• Time in Patent Office: 517 Days
• Field of Search: 701/1, 701/101, 701/36, 701/24, 701/29, 701/33, 714/4, 714/49, 711/154, 395/728
• US Class Current: 701/1
• CPC Class Codes: G05B 19/0421 Multiprocessor system

Abstract

A method and an apparatus for controlling operations in a vehicle, at least two processors accessing at least one memory device and a simultaneous read and/or write access of the at least two processors to the identical address of the memory device during program execution being prevented. The identical address is detected by way of an address comparison, and as a function of this address comparison a signal is transmitted to at least one processor. In particular, a first signal is transmitted to a first processor and a second signal to a second processor. Program execution by at least one of the at least two processors is thereby brought to a halt by the signal, or the respective processor is halted.

Claims

1. A method for controlling operations in a vehicle, comprising the steps of:

performing an address comparison to detect an identical address of a first operation by a first of at least two processors accessing at least one memory device and of a second, simultaneous operation by a second of the at least two processors accessing the at least one memory device, each of the first and second operations being one of a read operation and a write operation;

transmitting at least one signal to at least one of the first and second processors as a function of the address comparison; and

halting a program execution by the at least one of the first and second processors in response to the at least one signal, in order to prevent a simultaneous access of the first and second processors to the identical address of the at least one memory device during program execution.

2. The method according to claim 1, wherein the at least one signal includes a first signal transmitted to the first processor and a second signal transmitted to the second processor, the program execution of at least one of the first and second processors being halted by at least one of the first and second signals.

3. The method according to claim 1, wherein the program execution by the at least one of the first and second processors is halted by the at least one signal until at least one of (a) different addresses are detected in the address comparison and (b) the access of the other of the first and second processors is complete.

4. The method according to claim 1, wherein the program execution is halted by the at least one signal for a time that is based on the address comparison.

5. The method according to claim 1, wherein accesses to addresses of the at least one memory device during program execution by the first and second processors occur asynchronously, at any desired points in time.

6. The method according to claim 1, wherein the program execution by the second processor is halted if access of the first processor to the identical address simultaneously is detected before access of the second processor on the basis of the address comparison.

7. An apparatus for controlling operations in a vehicle, comprising:

at least two processors including a first processor and a second processor;

at least one memory device;

means for performing an address comparison to detect an identical address of a first operation by the first processor accessing the at least one memory device and of a second, simultaneous operation by the second processor accessing the at least one memory device, each of the first and second operations being one of a read operation and a write operation;

means for transmitting a first signal to the first processor and a second signal to the second processor as a function of the address comparison; and

means for halting a program execution by at least one of the first and second processors in response to at least one of the first and second signals, in order to prevent a simultaneous access of the first and second processors to the identical address of the at least one memory device during program execution.