Hardware and software co-verification employing deferred synchronization

• US 6,356,862 B2
• Filed: 09/24/1998
• Issued: 03/12/2002
• Est. Priority Date: 09/24/1998
• Status: Expired due to Term

• Current Assignee: Mentor Graphics Corporation (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Bailey, Brian
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): PHAN, THAI Q
• Application Number:
  US09/160,368
• Publication Number:
  US 20010011210A1
• Time in Patent Office: 1,265 Days
• Field of Search: 703/16, 703/20, 703/22, 703/26, 703/15, 703/19, 716/5
• US Class Current: 703/16
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

Hardware and software of a system is co-verified with synchronization events generated in the respective hardware and software verifications being accumulated and provided to the other verification on a periodic basis. The faster verification is halted to allow the slower verification to catch up, upon expiration of a synchronization window. Once caught up, the accumulated synchronization events are provided to the respective other verification. The transferred synchronization events are then in turn injected into the other verification at the same offset time into a synchronization period the synchronization events occurred in the previous synchronization period.

Claims

1. A method comprising:

accumulating first synchronization events of a verification of a software execution within a system; and

periodically, providing the accumulated first synchronization events to a verification of a hardware portion of the system, and receiving accumulated second synchronization events of the verification of the hardware portion of the system.

2. The method of claim 1, wherein said accumulating of first synchronization events includes storing the first synchronization events in a first organized data structure, and said receiving of accumulated second synchronization events of the verification of the hardware portion of the system includes storing the second synchronization events in a second organized data structure.

3. The method of claim 1, wherein said accumulating of first synchronization events includes accumulating first memory writing operations generated by the verification of the software execution within the system.

4. The method of claim 1, wherein the providing of accumulated first synchronization events and receiving of accumulated second synchronization events are performed at predetermined synchronization intervals.

5. The method of claim 4, wherein the method further includes configuring the size of the predetermined synchronization interval.

6. The method of claim 5, wherein said configuring includes configuring the size of the predetermined synchronization interval from a first smaller size to a second larger size.

7. The method of claim 5, wherein said configuring includes configuring the size of the predetermined synchronization interval from a first larger size to a second smaller size.

8. The method of claim 7, wherein said configuring from a first larger size to a second smaller size includes reducing the predetermined synchronization interval to where a last event to be synchronized transpired.

9. The method of claim 7, wherein said configuring from a first larger size to a second smaller size includes compressing verification time by a compression ratio.

10. The method of claim 7, wherein said configuring further includes repeating said configuring from a first larger size to a second smaller size with incrementally smaller sizes.

11. The method of claim 1, wherein the method further comprises injecting the received accumulated second synchronization events into the verification of the software execution within the system at corresponding timing offsets into a current synchronization frame.

12. An apparatus comprising:

a flow detector to monitor, detect and accumulate first synchronization events of a verification of a software execution within a system; and

a synchronizer coupled to the flow detector to periodically provide the accumulated first synchronization events to a verification of a hardware portion of the system, and receive accumulated second synchronization events of the verification of the hardware portion of the system.

13. The apparatus of claim 12, wherein the flow detector includes a first organized data structure for accumulating the first synchronization events, and a second organized data structure for storing the received accumulated second synchronization events of the verification of the hardware portion of the system.

14. The apparatus of claim 12, wherein the flow detector injects the received accumulated second synchronization events into the verification of the software execution within the system at corresponding timing offsets into a current synchronization frame.

15. The apparatus of claim 12, wherein the synchronizer provides the accumulated first synchronization events and receives the accumulated second synchronization events at predetermined synchronization intervals.

16. The apparatus of claim 15, wherein the apparatus further includes a configurator to configure/reconfigure the size of the predetermined synchronization interval.

17. The apparatus of claim 16, wherein the configurator is also used to compress verification time by a compression ratio.

18. The apparatus of claim 12, wherein the apparatus further includes a selected one of an instruction set simulator and a set of compiled code, coupled to the flow detector, to perform said verification of the software execution within the system.

19. The apparatus of claim 12, wherein the apparatus further includes a transaction level simulator coupled to the synchronizer to perform the verification of the hardware portion of the system.

20. The apparatus of claim 19, wherein the apparatus further includes

a selected one of an instruction set simulator and a set of compiled code, coupled to the flow detector, to perform said verification of the software execution within the system.

a selected one of a logic simulator and emulator to perform a second verification of the hardware portion of the system; and

an optimizing coordinator coupled to the selected one of the instruction set simulator and the set of compiled code, and to the selected one of the logic simulator and emulator, to optimize certain memory accesses performed by the verification of the software execution within the system and the second verification of the hardware portion of the system.

21. A storage medium having stored therein a plurality of programming instructions that are logically related to each other in such a manner, that when executed by a processor, the programming instructions accumulate first synchronization events of a verification of a software execution within a system, and periodically, provide the accumulated first synchronization events to a verification of a hardware portion of the system, and receive accumulated second synchronization events of the verification of the hardware portion of the system.

22. The storage medium of claim 21, wherein the programming instructions provide the accumulated first synchronization events and receive the accumulated second synchronization events at predetermined synchronization intervals.

23. The storage medium of claim 22, wherein the programming instructions further configure the size of the predetermined synchronization interval.

24. The storage medium of claim 23, wherein the programming instructions also compress verification time by a compression ratio.

25. The storage medium of claim 21, wherein the programming instructions also inject the received accumulated second synchronization events at corresponding offsets into a current synchronization frame.

26. A method comprising:

coordinating a verification of a software execution within a system and a first verification of a hardware portion of a system employing a deferred synchronization approach to enhance performance of the verification of the software execution within the system and the first verification of the hardware portion of the system; and

coordinating the verification of the software execution within the system and a second verification of the hardware portion of the system employing optimization to certain memory accesses to enhance performance of the verification of the software execution within the system and the second verification of the hardware portion of the system.

27. The method of claim 26, wherein the coordinating of the verification of the software execution within the system and the first verification of the hardware portion of the system includes accumulating first synchronization events of the verification of the software execution within the system, and periodically, providing the accumulated first synchronization events to the first verification of the hardware portion of the system, and receiving accumulated second synchronization events of the first verification of the hardware portion of the system.

28. The method of claim 27, wherein the periodic providing of the accumulated first synchronization events to the first verification of the hardware portion of the system, and receiving of the accumulated second synchronization events of the first verification of the hardware portion of the system are performed at predetermined synchronization intervals.

29. The method of claim 27, wherein the coordinating of the verification of the software execution within the system and the first verification of the hardware portion of the system further includes injecting the received accumulated second synchronization events of the first verification of the hardware portion of the system into the verification of the software execution within the system at corresponding offsets into a current predetermined synchronization interval.

30. An apparatus comprising:

a first coordinator to coordinate a verification of a software execution within a system and a first verification of a hardware portion of the system employing a deferred synchronization approach to enhance performance of the verification of the software execution within the system and first verification of the hardware portion of the system; and

a second coordinator to coordinate the verification of the software execution within the system and a second verification of the hardware portion of the system employing optimization to certain memory accesses to enhance performance of the verification of the software execution within the system and the second verification of the hardware portion of the system.

31. The apparatus of claim 30, wherein the first coordinator includes a flow detector to monitor, detect and accumulate first synchronization events of the verification of the software execution within the system, and a synchronizer coupled to the flow detector, to periodically provide the accumulated first synchronization events to the first verification of the hardware portion of the system, and receive accumulated second synchronization events of the first verification of the hardware portion of the system.

32. The apparatus of claim 31, wherein the apparatus further comprises a configurator to configure a size for a predetermined synchronization interval to periodically perform said providing of the accumulated first synchronization events to the first verification of the hardware portion of the system, and said receiving of the accumulated second synchronization events of the first verification of the hardware portion of the system.

33. The apparatus of claim 31, wherein the flow detector injects the received accumulated second synchronization events of the first verification of the hardware portion of the system into the verification of the software execution within the system at corresponding offsets into a current predetermined synchronization interval.

34. The apparatus of claim 30, wherein the apparatus further includes a selected one of an instruction set simulator and a set of compiled code, coupled to the flow detector, to perform said verification of the software execution within the system.

35. The apparatus of claim 30, wherein the apparatus further includes a transaction level simulator couple to the synchronizer to perform the verification of the hardware portion of the system.

36. The apparatus of claim 30, wherein the apparatus further includes:

a selected one of an instruction set simulator and a set of compiled code, coupled to the flow detector, to perform the verification of the software execution within the system;

a selected one of a logic simulator and emulator to perform the second verification of the hardware portion of the system; and

an optimizing coordinator coupled to the selected one of the instruction set simulator and the set of compiled code, and to the selected one of the logic simulator and emulator, to optimize certain memory accesses performed by the verification of the software execution within the system and second verification of the hardware portion of the system.