Hardware and software co-verification employing deferred synchronization
First Claim
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1. A method comprising:
- accumulating first synchronization events of a verification of a software execution within a system; and
periodically, providing the accumulated first synchronization events to a verification of a hardware portion of the system, and receiving accumulated second synchronization events of the verification of the hardware portion of the system.
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Abstract
Hardware and software of a system is co-verified with synchronization events generated in the respective hardware and software verifications being accumulated and provided to the other verification on a periodic basis. The faster verification is halted to allow the slower verification to catch up, upon expiration of a synchronization window. Once caught up, the accumulated synchronization events are provided to the respective other verification. The transferred synchronization events are then in turn injected into the other verification at the same offset time into a synchronization period the synchronization events occurred in the previous synchronization period.
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Citations
36 Claims
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1. A method comprising:
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accumulating first synchronization events of a verification of a software execution within a system; and
periodically, providing the accumulated first synchronization events to a verification of a hardware portion of the system, and receiving accumulated second synchronization events of the verification of the hardware portion of the system. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An apparatus comprising:
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a flow detector to monitor, detect and accumulate first synchronization events of a verification of a software execution within a system; and
a synchronizer coupled to the flow detector to periodically provide the accumulated first synchronization events to a verification of a hardware portion of the system, and receive accumulated second synchronization events of the verification of the hardware portion of the system. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
a selected one of an instruction set simulator and a set of compiled code, coupled to the flow detector, to perform said verification of the software execution within the system. a selected one of a logic simulator and emulator to perform a second verification of the hardware portion of the system; - and
an optimizing coordinator coupled to the selected one of the instruction set simulator and the set of compiled code, and to the selected one of the logic simulator and emulator, to optimize certain memory accesses performed by the verification of the software execution within the system and the second verification of the hardware portion of the system.
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- 21. A storage medium having stored therein a plurality of programming instructions that are logically related to each other in such a manner, that when executed by a processor, the programming instructions accumulate first synchronization events of a verification of a software execution within a system, and periodically, provide the accumulated first synchronization events to a verification of a hardware portion of the system, and receive accumulated second synchronization events of the verification of the hardware portion of the system.
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26. A method comprising:
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coordinating a verification of a software execution within a system and a first verification of a hardware portion of a system employing a deferred synchronization approach to enhance performance of the verification of the software execution within the system and the first verification of the hardware portion of the system; and
coordinating the verification of the software execution within the system and a second verification of the hardware portion of the system employing optimization to certain memory accesses to enhance performance of the verification of the software execution within the system and the second verification of the hardware portion of the system. - View Dependent Claims (27, 28, 29)
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30. An apparatus comprising:
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a first coordinator to coordinate a verification of a software execution within a system and a first verification of a hardware portion of the system employing a deferred synchronization approach to enhance performance of the verification of the software execution within the system and first verification of the hardware portion of the system; and
a second coordinator to coordinate the verification of the software execution within the system and a second verification of the hardware portion of the system employing optimization to certain memory accesses to enhance performance of the verification of the software execution within the system and the second verification of the hardware portion of the system. - View Dependent Claims (31, 32, 33, 34, 35, 36)
a selected one of an instruction set simulator and a set of compiled code, coupled to the flow detector, to perform the verification of the software execution within the system;
a selected one of a logic simulator and emulator to perform the second verification of the hardware portion of the system; and
an optimizing coordinator coupled to the selected one of the instruction set simulator and the set of compiled code, and to the selected one of the logic simulator and emulator, to optimize certain memory accesses performed by the verification of the software execution within the system and second verification of the hardware portion of the system.
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Specification