Microprocessor having an on-chip CPU fetching a debugging routine from a memory in an external debugging device in response to a control signal received through a debugging port

• US 6,356,960 B1
• Filed: 11/09/2000
• Issued: 03/12/2002
• Est. Priority Date: 10/29/1997
• Status: Expired due to Term

• Current Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Original Assignee: SGS Thomson Microelectronics Ltd (STMicroelectronics NV)
• Inventors: Jones, Andrew Michael, May, Michael David, Edwards, David Alan
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Park, Ilwoo
• Application Number:
  US09/710,775
• Time in Patent Office: 488 Days
• Field of Search: 710/4, 710/5, 710/71, 700/26, 717/4, 712/227, 714/30, 714/34, 714/35
• US Class Current: 710/5
• CPC Class Codes: G06F 11/3656 using a specific debug interface

Abstract

There is disclosed a computer system including a microprocessor on an integrated circuit chip comprising an on-chip CPU and a debugging port connected to a communication bus on the integrated circuit and to an external debugging computer device. The external debugging device is operable to transmit control signals through the debugging port: a) to stop execution by the CPU of instructions obtained from a first on-chip memory; b) to provide from a second memory associated with the external debugging computer device a debugging routine to be executed by the CPU; and c) to restart operation of the CPU after the routine with execution of instructions from an address determined by the external debugging device. The on-chip CPU is operable with code in the first memory which is independent of the debugging routine. A method of operating such a computer system with an external debugging device is also disclosed.

Claims

1. A computer system including a microprocessor on an integrated circuit chip comprising an on-chip CPU with a plurality of registers and a communication bus providing a parallel communication path between said CPU and a first memory local to said CPU, said first memory storing instructions for operation of said CPU, said integrated circuit device further comprising a debugging port connected to said bus on the integrated circuit chip and to an external debugging computer device having a second memory, said chip having circuitry responsive to first, second and third control signals from said external debugging device via said debugging port whereby said first control signal stops execution by the CPU of instructions obtained from said first memory, said second control signal causes said CPU to fetch from said second memory a debugging routine to be executed by the CPU and said third control signal restarts operation of the CPU after said debugging routine with execution of instructions from an address determined by said external debugging device, whereby said instructions in said first memory are independent of said debugging routine.

2. A computer system according to claim 1 in which said circuitry of said chip comprises logic circuitry operable to suspend execution of an instruction sequence by said CPU, said logic circuitry having an address store for holding an instruction location address for use in resuming execution of instructions by the CPU, said logic circuitry being connected to said communication bus whereby the logic circuitry may receive a signal packet from said external computer device through said debugging port.

3. A computer system according to claim 2 in which said CPU includes an instruction pointer circuit for indicating a next fetch address in execution of an instruction sequence and said address store of said logic circuitry is operable to change the pointer value in said instruction pointer circuit in response to a signal packet from said external computer device.

4. A computer system according to claim 3 in which said pointer circuit is operable to point to addresses in either of said first or second memories.

5. A computer system according to claim 1 in which said CPU and said external computer device are arranged to communicate with bit packets having a bit parallel form on said communication bus.

6. A computer system according to claim 5 in which said bit packets comprise request packets for sending from a packet source to a destination, said source and destination being both connected to said communication bus, and response packets for return from a said destination to a said source.

7. A computer system according to claim 5 in which said debugging port includes packet format translation circuitry for changing bit packets between a bit parallel on-chip format to a less parallel external format.

8. A computer system according to claim 7 in which said external format is bit serial.

9. A computer system according to claim 1 in which said first memory has software for execution by said on-chip CPU and said second memory has software for execution by said on-chip CPU in a debugging routine and additional software for execution by said external computer device in carrying out a debugging routine for said on-chip CPU.

10. A computer system according to claim 1 in which said single integrated circuit chip has a plurality of CPUs on the same chip each connected to said communication bus.

11. A computer system according to claim 10 wherein each CPU is arranged to include said debugging port in its address space.

12. A method of operating a computer system which comprises a microprocessor on an integrated circuit chip with an on-chip CPU, a plurality of registers and a communication bus providing a parallel communication path between said CPU and a first memory local to said CPU, said integrated circuit device having a debugging port connected to said bus and to an external debugging computer device having a second memory, said method comprising:

operating said CPU using instructions stored in said first memory; and

transmitting first, second and third control signals from said external debugging device through said debugging port wherein said first control signal stops (a) execution by the CPU of instructions obtained from said first memory, said second control signal causes said CPU to fetch (b) a debugging routine from said second memory and said third control signal restarts operation of the CPU after said debugging routine with execution of instructions from an address determined by said external debugging device.

13. A method according to claim 12 wherein, in response to control signals through said debugging port from said external debugging device, logic circuitry connected to said on-chip CPU operates to suspend execution of an instruction sequence by said CPU, store in an address store for said CPU an instruction location address for use in resuming execution of instructions by the CPU and cause said CPU to resume execution of an instruction sequence determined by said address store after execution of said debugging routine.

14. A method according to claim 13 in which instructions executed by the CPU are determined by a fetch address held in an instruction pointer circuit and said logic circuitry operates in response to a control signal through said debugging port to change the pointer value in said instruction pointer circuit.

15. A method according to claim 12 in which communications on said communication bus are effected in bit parallel format and said debugging port includes translation circuitry which translates packets to a less parallel external format.

16. A method according to claim 15 in which said external format is bit serial.

17. A method according to claim 12 in which communications on said communication bus include request packets for sending from a packet source to a destination, both connected to said bus, and response packets for return from a said destination to a said source.

18. A method according to claim 12 in which said first memory holds software for execution by said on-chip CPU and said second memory has software for execution by said on-chip CPU in a debugging routine, said software being transferred from said second memory to said first memory prior to execution by the CPU in a debugging routine.

19. A method system according to claim 12 in which said second memory includes software which is executed by said external computer device in carrying out a debugging routine for said on-chip CPU.

20. A method according to claim 12 in which a plurality of CPUs are provided on said single integrated circuit chip and a debugging routine is carried out on one of said CPUs as a result of control signals through said debugging port from said external debugging computer device while another of said CPUs on said integrated circuit device executes normal code derived from a first memory local to said CPU.

21. A method according to claim 12 in which a plurality of CPUs are provided on said integrated circuit device each having access to local first memory circuitry, one of said CPUs executing code from said first memory circuitry in order to effect debugging of code executed by another one of said CPUs on the same integrated circuit device.