Apparatus and method for pipelined memory operations

• US 6,356,975 B1
• Filed: 10/09/1998
• Issued: 03/12/2002
• Est. Priority Date: 10/10/1997
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Dillon, by Nancy David, Barth, Richard M., Tsern, Ely K., Hampel, Craig E., Stark, Donald C., Ware, Frederick A., Horowitz, Mark A., Dillon, John B.
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US09/169,526
• Time in Patent Office: 1,250 Days
• Field of Search: 711/5, 711/105, 711/150, 711/154, 711/167, 711/168, 711/169, 711/103, 711/149, 365/233, 365/189.02, 365/190, 365/230.05, 365/203
• US Class Current: 711/105
• CPC Class Codes: G06F 13/1615 using a concurrent pipeline structrure
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

Claims

1. A memory device comprising:

a memory core;

a plurality of external connections; and

interface circuitry coupled to said plurality of external connections to receive information specifying an operation to be performed on said memory core and coupled to said memory core to perform operations on said memory core, wherein said interface circuitry includes

a plurality of control operation units, and at least one data transfer operation unit, wherein said plurality of control operation units, said at least one data transfer operation unit and said memory core are configured to form a conflict-free pipeline for performing a universal sequence of operations on said memory core, wherein all memory device transactions that can be handled by said memory device can be processed using said universal sequence of operations.

2. The memory device of claim 1,

wherein said memory core is a conventional dynamic memory core,

wherein said universal sequence for said conventional dynamic core includes precharge, sense, transfer, and close operations, and

wherein said plurality of control operation units each comprises:

a sense operation unit a precharge operation unit, a close operation unit, a write operation unit, a read operation unit, a write data operation unit and a read data operation unit.

3. A dynamic random access memory device, comprising:

a dynamic random access memory core;

a plurality of external connections; and

interface circuitry coupled to said plurality of external connections to receive row and column operation information and to transfer data packets, wherein said interface circuitry is configured to receive row and column operation information separate from the transfer of data packets, wherein said interface circuitry is coupled to said memory core to perform operations on said memory core, and wherein said interface circuitry includes;

a sense operation unit,

a precharge operation unit, and

at least one data transfer operation unit,

wherein said sense and precharge operation units, said at least one data transfer operation unit and said memory core are configured to form a pipeline having distinct precharge, sense and transfer stages that are interconnected to form the pipeline and to perform sequences of precharge, sense and transfer operations executed without conflicts.

4. A dynamic random access memory device comprising:

a dynamic random access memory core for storing data information;

a plurality of external connections for receiving row operation information, column operation information and data information, said row operation information including sense commands, said column operation information including read commands and write commands, said plurality of external connections including

a first subset of external connections for receiving sense commands,

a second subset of external connections for receiving read commands and write commands, and

a third subset of external connections for transferring data information;

wherein the first, second and third subsets of external connections are distinct, non-overlapping subsets of the external connections, the sense commands received by the first subset of external connections include row address information, and the read commands and write commands received by the second subset of external connections include column address information; and

interface circuitry coupled to said plurality of external connections and said memory core, said interface circuitry configured to generate row timing signals and column timing signals to operate on said memory core in response to said received row operation information and said column operation information.

5. The memory device of claim 4, wherein

the sense commands include row address information, the read and write commands include column address information, and the row address information in a particular sense command and the column address information in a particular read or write command are used by the memory device to access a corresponding particular memory cell in the memory core.

6. The memory device of claim 4, wherein

the interface circuitry is configure to receive the sense commands via the first subset of external connections as a first temporal sequence of bits.

7. The memory device of claim 6, wherein

the interface circuitry is configure to receive the read and write commands via the second subset of external connections as a second temporal sequence of bits.

8. A memory device comprising:

a memory core;

a plurality of connectors configured for coupling to external connections; and

interface circuitry coupled to said plurality of connectors to receive information specifying an operation to be performed on said memory core and coupled to said memory core to perform operations on said memory core, wherein said interface circuitry includes

a plurality of control operation units, and at least one data transfer operation unit, wherein said plurality of control operation units, wherein said at least one data transfer operation unit and said memory core are configured to form a conflict-free pipeline having multiple, sequentially ordered pipeline stages for performing a universal sequence of operations on said memory core;

wherein said pipeline is configured to advance a given transaction in the pipeline by skipping one or more of said pipeline stages when predefined stage skipping conditions are satisfied, the given transaction requiring fewer operations than the operations in the universal sequence of operations, thereby reducing latency for the given transaction compared with a default latency associated with the given transaction being sequentially processed by all of said pipeline stages.

9. The memory device of claim 8,

wherein said memory core is a conventional dynamic memory core;

wherein said universal sequence for said conventional dynamic core includes precharge, sense, transfer, and close operations, and

wherein said plurality of control operation units each comprises;

a sense operation unit, a precharge operation unit, a close operation unit, a write operation unit, a read operation unit, a write data operation unit and a read data operation unit.

10. A memory device comprising:

a memory core;

a plurality of external connections; and

interface circuitry coupled to said plurality of external connections to receive information specifying an operation to be performed on said memory core and coupled to said memory core to perform operations on said memory core, wherein said interface circuitry includes

a plurality of control operation units, and at least one data transfer operation unit, wherein said plurality of control operation units, said at least one data transfer operation unit and said memory core are configured to form a conflict-free pipeline for performing a universal sequence of operations on said memory core;

wherein said pipeline is configured to allow sequences shorter than said universal sequence of operations for a given transaction by entering said conflict-free pipeline at a stage other than a starting stage of said conflict-free pipeline or by leaving said conflict-free pipeline at a stage other than an ending stage, and latency for said given transaction is decreased from a default latency associated with the conflict-free pipeline.

11. The memory device of claim 10,

wherein said memory core is a conventional dynamic memory core,

wherein said universal sequence for said conventional dynamic core includes precharge, sense, transfer, and close operations, and

wherein said plurality of control operation units each comprises:

a sense operation unit, a precharge operation unit, a close operation unit, a write operation unit, a read operation unit, a write data operation unit and a read data operation unit.

12. A method of operating a memory device comprising the steps of:

receiving sense commands on a first subset of external connections;

receiving read and write commands on a second subset of external connections; and

transferring data on a third subset of external connections, wherein each of said subsets of external connections receives information independent of other subsets of external connections;

wherein the first, second and third subsets of external connections are distinct and non-overlapping, the sense commands received on the first subset of external connections include row address information, and the read commands and write commands received by the second subset of external connections include column address information.

13. The method of claim 12, including accessing a memory cell within a memory core of the memory device in response to address information and command information provided in part by a particular sense command received via the first subset of external connections and in part by a read or write command received via the second subset of external connections.

14. A method of operating a dynamic random access memory device comprising the steps of:

receiving row and column operation information separately from the transfer of data packets, wherein said row operation information includes sense information and precharge operation information, wherein said column operation information includes data transfer information; and

processing said sense and precharge operation information and data transfer information in a pipelined manner such that sequences having an order of sense, transfer and precharge operations occur without stalling said pipeline.

15. The method of claim 14, wherein processing said sense and precharge operation information and data transfer information in a pipelined manner includes performing said sense, transfer and precharge operations in successive time slots.