Methods and apparatus for instruction addressing in indirect VLIW processors

• US 6,356,994 B1
• Filed: 07/09/1999
• Issued: 03/12/2002
• Est. Priority Date: 07/09/1998
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: BOPS, Inc. (Intel Corporation)
• Inventors: Pechanek, Gerald G., Barry, Edwin F.
• Primary Examiner(s): An, Meng-Al T.
• Assistant Examiner(s): EL HADY, NABIL M
• Application Number:
  US09/350,191
• Time in Patent Office: 977 Days
• Field of Search: 712/11, 712/18, 712/20, 712/24, 712/200, 712/210
• US Class Current: 712/24
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/32 Address formation of the next instruction, e.g. by incrementing the instruction counter G06F9/38 takes precedence
• CPC Class Codes: G06F 9/3552 using wraparound, e.g. modulo or circular addressing
• CPC Class Codes: G06F 9/3557 using program counter as base address
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3853 of compound instructions

Abstract

An indirect VLIW (iVLIW) architecture is described which contains a minimum of two instruction memories. The first instruction memory (SIM) contains short-instruction-words (SIWs) of a fixed length. The second instruction memory (VIM), contains very-long-instruction-words (VLIWs) which allow execution of multiple instructions in parallel. Each SIW may be fetched and executed as an independent instruction by one of the available execution units. A special class of SIW is used to reference the VIM indirectly to either execute or load a specified VLIW instruction (called an “XV” instruction for “eXecute VLIW”, or LV for “Load VLIW”). In these cases, the SIW instruction specifies how the location of the VLIW is to be accessed. Other aspects of this approach relate to the application of data memory addressing techniques for execution or loading of VLIWs that parallel the addressing modes used for data memory accesses. These addressing techniques provide tremendous flexibility for VLIW instruction execution.

Claims

1. An apparatus including a plurality of addressing modes for providing indirect access to very long instruction words (VLIWs) allowing both sequential code and parallel operations in the form of VLIWs to be encoded efficiently, wherein the sequential code comprising a sequence of short instruction words (SIWs) including indirect VLIW SIWs is loaded as part of a single instruction stream, the apparatus comprising:

a short instruction memory fetch logic for fetching a short instruction word from a short instruction memory (SIM);

the short instruction memory storing the short instruction word, said short instruction word including a field defining an addressing mode associated with the short instruction word, wherein said addressing mode is one of the plurality of addressing modes for accessing the VLIW instruction;

an instruction decoder for decoding the short instruction word;

a VLIW instruction memory (VIM) for storing VLIW instructions;

a VLIW memory address unit (VIM AGU) for determining the addressing mode associated with the short instruction word;

VIM address registers; and

a VIM address generation mechanism for selecting a VLIW in said VIM by generating a VIM address according to the address mode associated with said short instruction word;

wherein said addressing mode associated with the short instruction word is one of said plurality of addressing modes;

a direct VIM addressing mode, a base plus offset addressing mode, an indirect/indexed addressing mode, a circular indexed addressing mode, or a processing element (PE) relative addressing mode.

2. The apparatus of claim 1 further comprising a VIM direct address mode apparatus having:

a first instruction register (IR1) for storing the short instruction word including direct address bits;

said VIM AGU operating to determine that the short instruction word in the first instruction register is a direct VIM addressing mode instruction and providing direct addressing mode control signals; and

said VIM address generation mechanism operating to receive the direct addressing mode control signals and the direct address bits from the first instruction register to produce a VIM address value.

3. The apparatus of claim 2 wherein the first instruction register is formatted into at least three major sections a first section for opcode which may include a VIM addressing mode option field, a second section for iVLIW options defining a function of an issued SIW, and a third section for a VIM direct address.

4. The apparatus of claim 1 further comprising a VIM base displacement addressing apparatus having:

a first instruction register (IR1) for storing the short instruction word defining a base-plus-displacement VIM addressing mode;

a plurality of base registers storing different base values;

said VIM AGU operating to select one of the plurality of base registers;

an adder for receiving a base value from the selected base register and to add an offset from said short instruction word to produce a result;

an adder result register for storing the adder result if the short instruction word is a first type of instruction; and

a selector for directly selecting the adder result for a VIM address if the short instruction word is a second type of instruction, and for selecting the stored adder result from the adder result register if the short instruction word is the first type of instruction.

5. The apparatus of claim 4 wherein the first type of instruction is a load VLIW instruction.

6. The apparatus of claim 4 wherein the second type of instruction is an execute VLIW instruction.

7. The apparatus of claim 4 wherein the selector is a multiplexer which is selectively controlled by a control signal from said VIM AGU.

8. The apparatus of claim 4 wherein the first instruction register stores a 32-bit execute VLIW (XV) base-plus-offset instruction including a plurality of enable mask bits and a plurality of offset bits.

9. The apparatus of claim 1 further comprising a VIM indirect/indexed address mode apparatus having:

a first instruction register (IR1) for storing an iVLIW instruction having at least one address register selection bit;

a plurality of address registers storing different address values, a particular one of the address registers selected based upon a calculation utilizing the at least one address register selection bit; and

said VIM address generation mechanism operating to generate the VIM address based upon the address value for the particular address register selected.

10. The apparatus of claim 9 further comprising an adder which adds a specified increment value to the value from the particular address register creating a result to be stored into the particular address register for future use.

11. An apparatus including a plurality of addressing mode instructions for providing indirect access to very long instruction words (VLIWs) allowing both sequential code and parallel operations in the form of VLIWs to be encoded efficiently, wherein the sequential code comprising a sequence of short instruction words (SIWs) containing compact instructions including indirect VLIW SIWs is loaded as part of a single instruction stream, the apparatus comprising:

a short instruction memory fetch logic for fetching a compact instruction from a short instruction memory (SIM);

an instruction decoder for decoding the compact instruction;

a VLIW instruction memory (VIM) for storing VLIW instructions;

a VLIW memory address unit (VIM AGU) for determining the addressing mode associated with the compact instruction;

VIM address registers;

a VIM address generation mechanism for selecting a VLIW in said VIM by generating a VIM address; and

a first instruction register (IR1) for storing said compact instruction including an identifying address bit or bits, wherein said VIM AGU operates to determine that the compact instruction in the first instruction register is one of said plurality of addressing mode instructions;

a direct VIM addressing mode instruction, a base plus offset addressing mod instruction, an indirect/indexed addressing mod instruction, a circular indexed addressing mode instruction, or a processing element (PE) relative addressing mode instruction, and to provide appropriate VIM addressing mode control signal.