Data processor with trie traversal instruction set extension

• US 6,356,999 B1
• Filed: 10/16/2000
• Issued: 03/12/2002
• Est. Priority Date: 06/15/1998
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Cashman, John D., Riley, Paul M., Goyette, Leo, Grummer, Grant, Bahr, Raymond G., Ye, Wei, Osler, Bruce P.
• Primary Examiner(s): Donaghue, Larry D.
• Application Number:
  US09/688,590
• Time in Patent Office: 512 Days
• Field of Search: 712/227, 712/204, 712/36, 712/300, 712/42, 704/500-504, 709/247, 382/240, 717/11, 379/93.08
• US Class Current: 712/209
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/324 in the data link layer [OSI layer 2], e.g. HDLC
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A programmable data communications device is provided to process multiple streams of data according to multiple protocols. The device is equipped with a co-processor including multiple, programmable processors allowing data to be operated on by multiple protocols. The programmable processors within the co-processor include extended instruction sets including instructions providing the operations of zero stuffing, CRC computation, partial compare, conditional move, and trie traversal. These instructions allow the processor(s) of the co-processor to more efficiently execute programs implementing data communications protocols. Since each processor is programmable, protocols standards which change may be accommodated. A network device equipped with the co-processor can handle multiple simultaneous streams of data and can implement multiple protocols on each data stream. The protocols can execute within the co-processor either independently of each other, or in conjunction with each other.

Claims

1. A processor comprising:

a first input receiving a first input data, a second input receiving a second input data, a third input receiving a third input data and a fourth input receiving a partial subtraction and conditional move instruction;

a logic unit coupled to the first input, the second input, the third input and the fourth input, the logic unit including activatible partial subtraction and conditional move circuitry which is activated upon receipt of the partial subtraction and conditional instruction and which performs a comparison between the first input data and the third input data, if the comparison results in the first input data being equal to the third input data then a down traversal state is set, if the comparison results in the first input data being greater than the third input data then the second input data is copied into a predefined location and no state is set, if the comparison results in the first input data being less than the third input data then an insertion state is set and the first input data is inserted into a trie data structure;

an output coupled to the logic unit, the output outputting the third input data in a predefined location, storing the first input data into the trie data structure and maintaining the down traversal state and the insertion state information; and

wherein the processor can be programmed to process one of many different instructions.

2. The processor of claim 1 wherein the partial subtraction and conditional move instruction executes on the logic unit as part of a protocol to perform compression on the data.

3. The processor of claim 1 wherein the partial subtraction and conditional move instruction executes on the logic unit as part of a protocol to perform decompression on the data.

4. The processor of claim 1 wherein the partial subtraction and conditional move instruction executes on the logic unit as part of a protocol to perform encryption on the data.

5. The processor of claim 1 wherein the partial subtraction and conditional move instruction executes on the logic unit as part of a protocol to perform decryption on the data.

6. A computer program product embodied on a computer readable medium and comprising partial subtraction and conditional move code that, when executed, causes a logic unit to perform the following:

receiving a first input data;

receiving a second input data;

receiving a third input data;

receiving a partial subtraction and conditional move instruction;

comparing the first input data and the third input data, if the comparison results in the first input data being equal to the third input data then a down traversal state is set, if the comparison results in the first input data being greater than the third input data then the second input data is copied into a predefined location and no state is set, if the comparison results in the first input data being less than the third input data then an insertion state is set and the first input data is inserted into a trie data structure;

outputting the third input data to a predefined location;

storing the first input data into the trie data structure;

maintaining the down traversal state and the insertion state information; and

wherein the logic unit can be programmed to process one of many different instructions.