Circuit for setting computer system bus signals to predetermined states in low power mode

• US 6,357,013 B1
• Filed: 03/17/1998
• Issued: 03/12/2002
• Est. Priority Date: 12/20/1995
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Reif, James R., DeSchepper, Todd J., Kelly, Philip C.
• Primary Examiner(s): WILEY, DAVID ARMAND
• Application Number:
  US09/042,914
• Time in Patent Office: 1,456 Days
• Field of Search: 713/300-340
• US Class Current: 713/324
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands

Abstract

A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode. In those modes, the memory controller in the CPU-PCI bridge is disabled to conserve power. The power management circuit performs the refresh cycles based off an external asynchronous clock. Further, the power management circuit drives certain PCI bus signals to a certain state to avoid leakage current due to the existence of a mixture of 3.3-bolt and 5-volt components connected to the PCI bus.

Claims

1. A computer system having a plurality of power states including at least one low power state, comprising:

a microprocessor coupled to a processor bus;

a second bus for carrying a plurality of bus signals;

a first bus device coupled to the second bus and operating off a first power supply voltage;

the first bus device including an input buffer operating off said first power supply voltage and coupled to receive bus signals from the second bus, said received bus signals having a high state level that is lower than the first power supply voltage such that leakage current flows through said input buffer in the presence of a received high state level bus signal; and

a bus controller coupled to the second bus, the bus controller responding to the computer system entering a low power state by driving said bus signals to be received by the input buffer to a zero state to significantly reduce leakage current through said input buffer.

2. The system of claim 1 wherein the first bus device comprises a video controller.

3. The system of claim 1 wherein the second bus is a PCI bus.

4. The system of claim 3 wherein the bus signals driven to the zero state include PCI address/data signals.

5. The system of claim 4 wherein the bus signals driven to the zero state further include PCI byte enable signals.

6. The system of claim 1 wherein the bus controller is embedded in a bridge circuit coupled between the processor bus and the second bus.

7. The system of claim 1 wherein one of the fist and second power supply voltages is about 3.3 volts.

8. The system of claim 1 wherein the first power supply voltage is about 5 volts and the high state level of said bus signals is about 3.3 volts.

9. The system of claim 1 wherein the computer system comprises a portable computer.

10. The system of claim 9 wherein the computer system further comprises an expansion base, the expansion base including a third bus which is coupled to the second bus when the portable computer is received by the expansion base.

11. The system of claim 10 wherein the second bus and the third bus each comprise a PCI bus.

17. The system of claim 1 and further comprising a hard disk drive coupled to communicate with the microprocessor and a modem coupled to communicate with the microprocessor.

12. A computer system having a plurality of states including at least one low power state, comprising:

a microprocessor coupled to a processor bus;

a second bus for carrying a plurality of bus signals;

a plurality of bus devices coupled to the second bus, each of the bus devices capable of controlling the second bus; and

a bus controller coupled to the second bus, the bus controller causing one of said plurality of bus devices to drive at least some of the bus signals to a zero state if the computer system is in the low power state.

13. The system of claim 12 wherein the bus controller is embedded in a bridge circuit coupled between the processor bus and the second bus.

14. The system of claim 12 wherein the second bus comprises a PCI bus.

15. The system of claim 12 wherein a first one of the bus devices operates off a first power supply voltage and a second one of the bus devices operates off a second power supply voltage, the second power supply voltage being greater than the first power supply voltage.

16. The system of claim 15 wherein the first power supply voltage is about 3.3 volts and the second power supply voltage is about 5 volts.

18. A method of managing power consumption in a computer system, the computer system having a bus operable to carry a plurality of bus signals, and a first bus device coupled to the bus, said first bus device inclusing an input buffer oprable from a first voltage level and coupled to receive from said bus, bus signals having a high state voltage level that is less than said first voltage level such that leakge current flows through said input buffer when a said high state voltage level bus signal is received by the input buffer, wherein the computer system has at least one low power state, and wherein the first bus device has ownership of the bus in the low power state, the method comprising the steps of:

detecting if the computer system has entered the low power state; and

responding to said detection by driving the bus signals to be received by said input buffer to a zero state.

19. The method of claim 18 wherein the first bus device operates off a first power supply voltage and the second bus device operates off a second power supply voltage, the second power supply voltage being greater than he first power supply voltage.

20. The method of claim 18 wherein the bus is a PCI bus.

21. The method of claim 18 and further comprising the step of monitoring the system for inactivity and causing the system to enter the lower power state in response to the monitoring step.

22. A computer system having a plurality of power states including at least one low power state, comprising:

a microprocessor coupled to a processor bus;

a PCI bus for carrying a plurality of PCI bus signals;

a bus device coupled to the PCI bus and operating off a first power supply voltage;

the bus device including an input buffer operating off said first power supply voltage and coupled to receive at least PCI address/data signals and PCI byte enable signals from the PCI bus, said received bus signals having a high state level that is lower than the first power supply voltage such that leakage current flows through said input buffer in the presence of a received high state level bus signal; and

a bus controller embedded in a bridge circuit coupled between the processor bus and the PCI bus, the bus controller responding to the computer system entering a low power state by driving said PCI address/data signals and PCI byte enable signals bus signals to a zero state to significantly reduce leakage current through said input buffer of the bus device.

23. The system of claim 22, wherein the PCI bus device is a video controller device.

24. The system of claim 23 wherein the first power supply voltage is about 5 volts and the high state level of said bus signals is about 3.3 volts.

25. The system of claim 22 wherein the computer system comprises a portable computer and an expansion base, the expansion base including a PCI bus which is coupled to the PCI bus of the portable computer when the portable computer is received by the expansion base.