Testing and burn-in of IC chips using radio frequency transmission

• US 6,357,025 B1
• Filed: 09/28/2000
• Issued: 03/12/2002
• Est. Priority Date: 11/20/1992
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Tuttle, Mark E.
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): LIN, SAMUEL K
• Application Number:
  US09/675,452
• Time in Patent Office: 530 Days
• Field of Search: 714/724, 714/733, 714/30
• US Class Current: 714/724
• CPC Class Codes: G01R 31/01 Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass production; Testing objects at points as they pass through a testing station testing of cables continuously passing the testing apparatus G01R31/59; testing dielectric strength or breakdown voltage G01R31/12
• CPC Class Codes: G01R 31/2822 of microwave or radiofrequency circuits of attenuation, gain, e.g. using network analyzers G01R27/28
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/303 of integrated circuits G01R31/305 - G01R31/315 take precedence
• CPC Class Codes: G06K 19/0701 at least one of the integrated circuit chips comprising an arrangement for power management
• CPC Class Codes: G06K 7/0095 Testing the sensing arrangement, e.g. testing if a magnetic card reader, bar code reader, RFID interrogator or smart card reader functions properly testing of electrical circuits G01R31/28

Abstract

A testing system evaluates one or more integrated circuit chips using RF communication. The system includes an interrogator unit with a radio communication range, and an IC chip adapted with RF circuitry positioned remotely from the interrogator unit, but within the radio communication range. The interrogator unit transmits a power signal to energize the IC chip during test procedures, and interrogating information for evaluating the operation of the IC chip. Test results are transmitted by the IC chip back to the interrogator unit for examination to determine whether the IC chip has a defect. In this is manner, one or more IC chips can be evaluated simultaneously without physically contacting each individual chip.

Claims

1. A testing system for evaluating a plurality of integrated circuit chips, comprising:

an interrogator unit having a radio communication range, the interrogator unit including data evaluation circuitry configured to transmit interrogating information via radio communication and to receive test data from the plurality of integrated circuits via radio communication; and

a plurality of integrated circuit chips respectively configured to be positioned within the radio communication range, respective integrated circuit chips including operational circuitry, and test interface circuitry being configured to receive the interrogating information from the data evaluation circuitry of the interrogator unit and to test cycle the operational circuitry according to the interrogating information, the test interface circuitry being configured to transmit, via radio communication, test data output by the operational circuitry in response to the interrogating information back to the data evaluation circuitry of the interrogator unit.

2. The testing system of claim 1, further comprising:

an RF isolating housing configured to hold the interrogator unit and the plurality of integrated circuit chips, the housing defining a chamber which allows radio communication between the interrogator unit and respective ones of the plurality of integrated circuit chips while blocking RF signals exterior to the housing from entering the chamber.

3. The testing system of claim 1, wherein the data evaluation circuitry of the interrogator unit is configured to:

examine the test data to determine for respective ones of the integrated circuit chips whether the chip is defective; and

provide an identification code as part of the interrogating information.

4. The testing system of claim 3, wherein respective integrated circuit chips further include a tag configured to store an ID label identifying respective ones of the plurality of integrated circuit chips, and wherein the test interface circuitry includes discriminating circuitry configured to compare the identification code sent by the data evaluation circuitry with the ID label stored by the tag, the test interface circuitry being configured to test cycle the operational circuitry when the identification code matches the ID label.

5. A testing system for evaluating a plurality of integrated circuit chips, comprising:

an interrogator unit having a radio communication range sufficient to include the plurality of integrated circuit chips, including;

power transfer circuitry configured to transmit via radio communication a power signal having a power inducing frequency and amplitude;

data evaluation circuitry configured to transmit interrogating information via radio communication and for receiving test data via radio communication;

a plurality of integrated circuit chips positioned remotely from the interrogator unit, but within the radio communication range, respective integrated circuit chips including;

operational circuitry;

power circuitry electrically coupled to the operational circuitry and configured to receive the power signal from the power transfer circuitry of the interrogator unit, the power circuitry generating power from the power signal and supplying the power to the operational circuitry; and

test interface circuitry electrically coupled to the operational circuitry and configured to receive the interrogating information from the data evaluation circuitry of the interrogator unit, the test interface circuitry being configured to test cycle the operational circuitry according to the interrogating information, the test interface circuitry being configured to transmit via radio communication test data output by the operational circuitry in response to the interrogating information back to the data evaluation circuitry of the interrogator unit.

6. The testing system of claim 5, further comprising an RF isolating housing configured to hold the interrogator unit and the plurality of integrated circuit chips, the housing defining a chamber that allows radio communication between the interrogator unit and respective ones of the plurality of integrated circuit chips while blocking RF signals exterior to the housing from entering the chamber.

7. The testing system of claim 5, wherein:

the power transfer circuitry is configured to transmit the power signal at a first frequency; and

the data evaluation circuitry is configured to transmit the interrogating information at a second frequency different than the first frequency.

8. The testing system of claim 5, wherein:

the power transfer circuitry is configured to transmit the power signal using a first transmission method; and

the data evaluation circuitry is configured to transmit the interrogating information using a second transmission method different than the first transmission method.

9. The testing system of claim 5, wherein:

the power transfer circuitry is configured to transmit the power signal at a first frequency;

the data evaluation circuitry is configured to transmit the interrogating information at a second frequency different than the first frequency; and

the test interface circuitry is configured to transmit the test data at a third frequency different than the first and second frequencies.

10. The testing system of claim 5, wherein:

the power transfer circuitry is configured to transmit the power signal using a first transmission method;

the data evaluation circuitry is configured to transmit the interrogating information using a second transmission method different than the first transmission method; and

the test interface circuitry is configured to transmit the test data using a third transmission method different than the first and second transmission methods.

11. The testing system of claim 5, wherein the data evaluation circuitry of the interrogator unit is configured to:

examine the test data to determine whether any of the plurality of integrated circuit chips has a defect; and

provide an identification code as part of the interrogating information.

12. The testing system of claim 11, wherein respective integrated circuit chips further include a tag configured to store an ID label identifying the integrated circuit chip, and wherein the test interface circuitry includes discriminating circuitry configured to compare the identification code sent by the data evaluation circuitry with the ID label stored by the tag, the test interface circuitry being configured to test cycle the operational circuitry when the identification code matches the ID label.

13. A testing system for evaluating a plurality of integrated circuit chips, comprising:

an RF isolated housing defining a chamber, the housing being configured to block RF signals originating external to the housing from entering the chamber;

an interrogator unit having a transmitting device provided in the housing and having a radio communication range allowing simultaneous communication with a plurality of integrated circuit chips, the interrogator unit including;

power transfer circuitry configured to transmit within the chamber via radio communication a power signal having a power inducing frequency and amplitude;

data evaluation circuitry configured to transmit identification codes and interrogating information within the chamber via radio communication and for receiving test data via radio communication;

multiple integrated circuit chips configured to be positioned within the chamber and remotely from the interrogator unit, but within the radio communication range, individual integrated circuit chips including;

operational circuitry;

power circuitry electrically coupled to the operational circuitry and configured to receive the power signal from the power transfer circuitry of the interrogator unit, the power circuitry being configured to generate power from the power signal and supply the power to the operational circuitry;

a tag for storing an ID label identifying the individual integrated circuit chip; and

test interface circuitry electrically coupled to the operational circuitry and including receiving circuitry configured to receive the interrogating information from the data evaluation circuitry of the interrogator unit and discriminating circuitry configured to compare the identification code sent by the data evaluation circuitry with the ID label stored by the tag, the test interface circuitry being configured to test cycle the operational circuitry according to the interrogating information in response to the identification code matching the ID label, the test interface circuitry further including transmitting circuitry configured to transmit via radio communication test data output by the operational circuitry in response to the interrogating information back to the data evaluation circuitry of the interrogator unit.

14. The testing system of claim 13, wherein:

the power transfer circuitry is configured to transmit the power signal at a first frequency; and

the data evaluation circuitry is configured to transmit the interrogating information at a second frequency different than the first frequency.

15. The testing system of claim 13, wherein:

the power transfer circuitry is configured to transmit the power signal using a first transmission method; and

the data evaluation circuitry is configured to transmit the interrogating information using a second transmission method different than the first transmission method.

16. The testing system of claim 13, wherein:

the power transfer circuitry is configured to transmit the power signal at a first frequency;

the data evaluation circuitry is configured to transmit the interrogating information at a second frequency different than the first frequency; and

the test interface circuitry is configured to transmit the test data at a third frequency different than the first and second frequencies.

17. The testing system of claim 13, wherein:

the power transfer circuitry is configured to transmit the power signal using a first transmission method;

the data evaluation circuitry is configured to transmit the interrogating information using a second transmission method different than the first transmission method; and

the test interface circuitry is configured to transmit the test data using a third transmission method different than the first and second transmission methods.

18. The testing system of claim 13, wherein the data evaluation circuitry is configured to examine the test data to determine whether any of the integrated circuit chips has a defect.

19. A method for testing a plurality of integrated circuit chips respectively having operational circuitry, the method comprising:

forming test interface circuitry in respective ones of the plurality of integrated circuit chips, the test interface circuitry being electrically coupled to the operational circuitry;

providing an interrogator unit having a radio communication range;

locating the plurality of integrated circuit chips remotely from the interrogator unit, but within the radio communication range;

powering the operational circuitry and the test interface circuitry;

transmitting interrogating information from the interrogator unit to the test interface circuitry on respective ones of the plurality of integrated circuit chips via radio communication;

test cycling the operational circuitry according to the interrogating information; and

transmitting test data output by the operational circuitry in response to the interrogating information back to the interrogator unit via radio communication.

20. The method of claim 19, further comprising examining the test data at the interrogator unit for respective integrated circuit chips to determine whether the integrated circuit chip has a defect.

21. The method of claim 19, further comprising:

marking respective integrated circuit chips with an ID label;

transmitting an identification code from the interrogator unit;

comparing the identification code with the ID label; and

test cycling the operational circuitry only when the identification code matches the ID label.

22. A method for testing a plurality of integrated circuit chips each having operational circuitry formed thereon, each having power circuitry formed thereon, each having operational circuitry formed thereon and each having test interface circuitry formed thereon, the power circuitry being electrically coupled to the operational circuitry and the test interface circuitry being electrically coupled to the operational circuitry, the method comprising:

providing an interrogator unit having a radio communication range;

locating the plurality of integrated circuit chips within the radio communication range;

transmitting a power signal having a power inducing frequency and amplitude from the interrogator unit to the power circuitry on each of the plurality of integrated circuit chips via radio communication;

generating power in each of the plurality of integrated circuit chips from the power signal;

supplying the power to the operational circuitry;

transmitting interrogating information from the interrogator unit to respective ones of the test interface circuitry via radio communication;

test cycling the operational circuitry according to the interrogating information; and

transmitting test data output by the operational circuitry in response to the interrogating information back to the interrogator unit via radio communication.

23. The method of claim 22, further comprising examining the test data at the interrogator unit to determine whether any of the plurality of integrated circuit chips has a defect.

24. The method of claim 22, further comprising transmitting the power signal and the interrogating information using a spread spectrum technique.

25. The method of claim 22, further comprising:

transmitting the power signal at a first frequency; and

transmitting the interrogating information at a second frequency different than the first frequency.

26. The method of claim 22, further comprising:

transmitting the power signal at a first frequency;

transmitting the interrogating information at a second frequency different than the first frequency; and

transmitting the test data at a third frequency different than the first and second frequencies.

27. The method of claim 22, further comprising:

marking respective integrated circuit chips with an ID label;

transmitting an identification code from the interrogator unit;

comparing the identification code with the ID label; and

test cycling the operational circuitry only when the identification code matches the ID label.