Method for producing semiconductor device, method for producing semiconductor laser device, and method for producing quantum wire structure

• US 6,358,316 B1
• Filed: 08/09/1995
• Issued: 03/19/2002
• Est. Priority Date: 09/10/1992
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Kimura, Tatsuya, Kizuki, Hirotaka, Hayafuji, Norio
• Primary Examiner(s): KUNEMUND, ROBERT M
• Application Number:
  US08/513,036
• Time in Patent Office: 2,414 Days
• Field of Search: 437/129, 437/90, 156/651.1, 117/105, 117/89, 117/954, 438/761, 438/29, 438/39, 438/40, 438/41
• US Class Current: 117/105
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: H01L 21/02107 Forming insulating materials on a substrate
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02395 Arsenides
• CPC Class Codes: H01L 21/02463 Arsenides
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/30621 Vapour phase etching
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/314 Inorganic layers H01L21/3105, H01L21/32 take precedence
• CPC Class Codes: H01L 29/66469 with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01S 5/2081 using special etching techniques
• CPC Class Codes: H01S 5/2231 with inner confining structure only between the active layer and the upper electrode
• CPC Class Codes: H01S 5/227 Buried mesa structure ; Striped active layer
• CPC Class Codes: H01S 5/2275 mesa created by etching
• CPC Class Codes: H01S 5/3203 on non-planar substrates to create thickness or compositional variations
• CPC Class Codes: H01S 5/32308 emitting light at a wavelength less than 900 nm
• CPC Class Codes: H01S 5/341 Structures having reduced dimensionality, e.g. quantum wires
• CPC Class Codes: H01S 5/3432 : the whole junction comprising only (AI)GaAs
• CPC Class Codes: H01S 5/4031 : Edge-emitting structures
• CPC Class Codes: H01S 5/4043 : with vertically stacked active layers

Abstract

In a method for producing a semiconductor device, a compound semiconductor cap layer including no aluminum is grown on a compound semiconductor layer including aluminum, a mask pattern insulating film is formed on a part of the compound semiconductor cap layer, the compound semiconductor wafer with the insulating mask pattern is immersed in an ammonium sulfide solution, the compound semiconductor wafer is selectively etched away using a chlorine containing gas in a reaction chamber, and a groove formed in the etching process is filled with a compound semiconductor layer grown in the reaction chamber by MOCVD. Therefore, a regrowth interface on which no impurity is segregated is attained, improving the quality of the regrown crystal layer.

Claims

1. A method for producing a semiconductor device comprising:

growing a compound semiconductor cap layer including no aluminum on a compound semiconductor layer including aluminum;

selectively forming a mask pattern comprising an insulating film on a part of the compound semiconductor cap layer;

immersing the compound semiconductor cap layer having the insulating mask pattern in an ammonium sulfide solution;

selectively etching the compound semiconductor cap layer using a chlorine-containing gas in a reaction chamber to form a groove; and

filling the groove with a compound semiconductor layer grown in the reaction chamber by MOCVD.

3. The method of claim 1 wherein the compound semiconductor layer including aluminum is AlGaAs and the compound semiconductor cap layer is GaAs.

2. A method for producing a semiconductor device comprising:

growing a compound semiconductor cap layer including no aluminum on a compound semiconductor layer including aluminum;

selectively forming a mask pattern comprising an insulating film on a part of the compound semiconductor cap layer;

removing an oxide film the compound semiconductor cap layer in a reaction chamber using one of a hydrogen plasma and exposure to ultraviolet light;

selectively etching the compound semiconductor cap layer using a chlorine-containing gas in a reaction chamber to form a groove; and

filling the groove with a compound semiconductor layer grown in the reaction chamber by MOCVD.

4. The method of claim 2 wherein the compound semiconductor layer including aluminum is AlGaAs and the compound semiconductor cap layer is GaAs.

5. A method for producing a semiconductor device including dry etching an Al_xGa₁₋

xAs (0≦

x≦

1) layer using a HCl gas, arsine gas, and hydrogen supplied at the same time with a partial pressure of the arsine gas in a range of from 8×

10<sup>−

3</sup> Torr to 0.08 Torr and a flow ratio of the arsine gas to the HCl gas in a range of from 0.25 to 2.5.

6. A method for fabricating a semiconductor laser comprising:

growing a plurality of Al_xGa<sub>1−

x</sub>As (0≦

x≦

1) layers on a {110} surface of a semiconductor substrate to form a laser diode structure;

forming an etching mask comprising an insulating film on a part of the laser diode structure; and

forming an oscillation facet of the laser diode with a {111}B surface perpendicular to the {110} surface of the semiconductor substrate by etching with HCl, arsine, and hydrogen supplied at the same time with a partial pressure of the arsine gas in a range from 8×

10<sup>−

3</sup> Torr to 0.08 Torr and a flow ratio of the arsine gas to the HCl gas in a range of from 0.25 to 2.5.

7. A method for producing a semiconductor device including etching a III-V compound semiconductor layer with a chlorine-containing gas, the etching process comprising:

placing a III-V compound semiconductor layer in a reactor;

a first step of introducing into the reactor respective pulses of a Group V gas and a chlorine-containing gas so that the duration of a pulse of the chlorine-containing gas is shorter than the duration of a pulse of the Group V gas, the chlorine-containing gas being introduced while the Group V gas in being introduced. to etch the III-V compound semiconductor layer;

a second step of, between pulses of the Group V gas, purging the reactor with hydrogen; and

alternatingly repeating the first and second steps to etch the III-V compound semiconductor layer.

8. The method of claim 7 wherein the Group V gas is AsH₃ and the chlorine-containing gas is HCl.

9. A method for producing a semiconductor device including etching a III-V compound semiconductor with a chlorine-containing gas, the etching process comprising:

preparing an apparatus having a rotatable discord susceptor with a surface;

partitioning the surface of the susceptor into at least first and second regions using flows of hydrogen;

filling the first region with a gas mixture comprising a Group V hydride gas, a chlorine-containing gas, and hydrogen;

filling the second region with hydrogen;

placing a III-V compound semiconductor layer on the susceptor;

first step of rotating the susceptor to place the III-V compound semiconductor layer in the first region filled with the gas mixture comprising the Group V hydride gas, the chlorine-containing gas, and hydrogen, thereby etching the III-V compound semiconductor layer;

a second step of rotating the susceptor to place the III-V compound semiconductor layer in the second region filled with hydrogen; and

alternatingly repeating the first and second steps to etch the III-V compound semiconductor layer.

10. The method of claim 9 wherein the Group V hydride gas is AsH₃ and the chlorine-containing gas is HCl.

11. A method for producing a quantum wire structure comprising:

forming a first semiconductor layer having an energy band gap on a semiconductor substrate with a {100} surface orientation;

forming an etching mask on the first semiconductor layer, the etching mask having a stripe-shaped opening extending along an <

011>

direction of the substrate;

etching the first semiconductor layer using HCl gas, arsine gas, and hydrogen introduced into a reactor at the same time with a partial pressure of the arsine gas in a range of from 8×

10<sup>−

3</sup> Torr to 0.08 Torr and a flow ratio of the arsine gas to the HCl gas in a range of from 0.25 to 2.5, thereby forming a stripe-shaped V groove with side surfaces that are {111}B planes;

forming a second semiconductor layer having an energy band gap smaller than the energy band gap of the first semiconductor layer in the vicinity of the bottom of the V groove; and

forming a third semiconductor layer having an energy band gap larger than the energy band gap of the second semiconductor layer on the second semiconductor layer.

12. A method for producing quantum wire structures comprising:

growing a first high-resistivity layer comprising a first semiconductor having an electron affinity on a semiconductor substrate;

successively growing a second high-resistivity layer comprising a second semiconductor having an electron affinity smaller than the electron affinity of the first semiconductor and a third high-resistivity layer comprising the first semiconductor;

forming alternating projections and recesses in the second high-resistivity layer, so that the cross-section of each recess is an inverted triangles by gas etching using HCl gas, arsine gas, and hydrogen introduced into a reactor at the same time with a partial pressure of the arsine gas in a range of from 8×

10<sup>−

3</sup> Torr to 0.08 Torr and a flow ratio of the arsine gas to the HCl gas in a range of from 0.25 to 2.5; and

successively growing a first n type layer comprising the second semiconductor and a second n type layer comprising the first semiconductor.

13. A method for fabricating a semiconductor laser comprising:

successively growing at least a first conductivity type Al_yGa<sub>1−

y</sub>As cladding layer, an Al_zGa<sub>1−

z</sub>As (0≦

z<

y) active layer, and a second conductivity type Al_wGa<sub>1−

w</sub>As (z<

w) cladding layer on a first conductivity type GaAs substrate with a {100} surface orientation;

forming a stripe-shaped insulating film pattern extending along a <

011>

direction on a part of the semiconductor substrate after the growing process;

removing an oxide film from the grown semiconductor layers using an ammonium sulfide solution;

using the insulating film pattern as a mask, selectively etching the grown semiconductor layers with a chlorine-containing gas, thereby forming a stripe-shaped ridge structure with side walls that are {111}B planes; and

growing a current blocking layer on opposite sides of the ridge structure.

14. The method of claim 13 including growing a high-resistivity or semi-insulating GaAs layer as the current blocking layer.

15. The method of claim 13 including successively growing a second conductivity type GaAs layer and a first conductivity type GaAs layer as the current blocking layer.

16. A method for fabricating a semiconductor laser comprising:

successively growing at least a first conductivity type Al_yGa<sub>1−

y</sub>As cladding layer, an Al_zGa<sub>1−

z</sub>As (0≦

z<

y) active layer, and a second conductivity type Al_wGa<sub>1−

w</sub>As (z<

w) cladding layer on a first conductivity type GaAs substrate with a {100} surface orientation;

forming a stripe-shaped insulating film pattern extending along a <

011>

direction on a part of the semiconductor substrate after the growing process;

removing an oxide film from the grown layers by cleaning in a reactor using one of a hydrogen plasma and ultraviolet light;

using the insulating film pattern as a mask, selectively etching the grown semiconductor layers with a chlorine-containing gas, thereby forming a stripe-shaped ridge structure with side walls that are {111}B planes; and

growing a current blocking layer on opposite sides of the ridge structure.

17. The method of claim 16 including growing a high-resistivity or semi-insulating GaAs layer as the current blocking layer.

18. The method of claim 16 including successively growing a second conductivity type GaAs layer and a first conductivity type GaAs layer as the current blocking layer.