Method for superior step coverage and interface control for high K dielectric capacitors and related electrodes

• US 6,358,810 B1
• Filed: 07/28/1998
• Issued: 03/19/2002
• Est. Priority Date: 07/28/1998
• Status: Expired due to Term

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Egermeier, John, Dornfest, Charles, Khurana, Nitin
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): BROPHY, JAMIE LYNN
• Application Number:
  US09/123,690
• Time in Patent Office: 1,330 Days
• Field of Search: 438/396, 438/393, 438/399, 438/652, 438/653, 438/686
• US Class Current: 438/396
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/60 Electrodes

Abstract

The present invention provides a multi-layer semiconductor memory device comprising: a bottom electrode having a bottom layer, an upper interface layer and an intermediate tuning layer disposed between the bottom layer and the upper interface layer; a top electrode; and a high dielectric constant dielectric layer disposed between the bottom electrode and the top electrode. The present invention further provides an apparatus and a method for manufacturing high density DRAMs having capacitors having high quality HDC materials and low leakage currents. Another aspect of the present invention provides an electrode-dielectric interface that nucleates high quality HDC films. The present invention further provides an apparatus and a method for manufacturing capacitors within a high aspect ratio aperture.

Claims

1. A method for forming a capacitor on a substrate, comprising:

a) depositing a bottom layer over a conductor plug in the substrate;

b) depositing a tuning layer over the bottom layer;

c) depositing an interface layer over the tuning layer;

d) re-sputtering the interface layer to conformally cover the tuning layer and the bottom layer;

e) depositing a high k dielectric layer over the interface layer, wherein the high k dielectric layer has a thickness of about 80 angstroms to about 800 angstroms; and

f) depositing an upper electrode layer over the dielectric layer.

2. A method for forming a capacitor in a high aspect ratio feature, comprising:

a) depositing a tuning layer in the feature by physical vapor deposition;

b) distributing and redepositing the tuning layer by high density plasma physical vapor deposition;

c) depositing an interface layer over the tuning layer by physical vapor deposition;

d) distributing and redepositing the interface layer by high density plasma physical vapor deposition;

e) depositing a high k dielectric layer over the interface layer, wherein the high k dielectric layer has a thickness of about 80 angstroms to about 800 angstroms; and

f) depositing an upper electrode layer over the high k dielectric layer.

3. The method of claim 2 wherein the tuning layer comprises a material selected from the group comprising ruthenium oxide, ruthenium combined with ruthenium oxide, iridium oxide, iridium combined with iridium oxide, titanium aluminum nitride and combinations thereof.

4. The method of claim 2 wherein the interface layer comprises a material selected from the group comprising platinum, ruthenium, iridium, rhodium, platinum combined with rhodium, platinum combined with iridium, platinum combined with ruthenium and combinations thereof.

5. The method of claim 2, further comprising:

g) depositing a barrier layer in the feature before depositing the tuning layer.

6. The method of claim 5 wherein the barrier layer comprises titanium, titanium nitride, titanium aluminum nitride, tantalum, tantalum nitride, tantalum aluminum nitride, and combinations thereof.

7. The method of claim 5 wherein the barrier layer is titanium aluminum nitride.

8. The method of claim 5 wherein the barrier layer has a thickness of about 50 angstroms to about 500 angstroms.

9. The method of claim 2 wherein the tuning layer has a thickness of about 50 angstroms to about 1,000 angstroms.

10. The method of claim 2 wherein the interface layer is a combination material comprising platinum combined with rhodium, platinum combined with iridium, platinum combined with ruthenium, and combinations thereof.

11. The method of claim 10 wherein the combination material comprises about 75% to about 90% platinum.

12. The method of claim 2 wherein the interface layer has a thickness of about 200 angstroms to about 4,000 angstroms.

13. The method of claim 2 wherein the high k dielectric layer comprises barium strontium titanate, lead zirconate titanate, lead lanthanium titanate, barium titanate, strontium titanate, and strontium bismuth titanate.

14. The method of claim 13 wherein the high k dielectric layer is doped.

15. The method of claim 2 wherein the high k dielectric layer has a thickness of about 200 angstroms to about 300 angstroms.

16. The method of claim 2 wherein the high k dielectric layer has a median grain thickness of less than 150 angstroms.

17. The method of claim 2 wherein the upper electrode layer comprises platinum, ruthenium, iridium, rhodium, platinum combined with rhodium, platinum combined with iridium, platinum combined with ruthenium, and combinations thereof.

18. A method for forming a capacitor on a substrate, comprising:

a) depositing a bottom layer over a conductor plug in the substrate;

b) depositing a barrier layer over the bottom layer;

c) depositing a tuning layer over the barrier layer;

d) depositing an interface layer over the tuning layer, wherein the tuning layer controls the microstructure of the interface layer;

e) depositing a high k dielectric layer over the interface layer; and

f) depositing an upper electrode layer over the dielectric layer.

19. A method for forming a capacitor on a substrate, comprising:

depositing a bottom layer over a conductor plug in the substrate;

depositing a barrier layer on the bottom layer;

depositing a tuning layer over the barrier layer by physical vapor deposition;

depositing an interface layer over the tuning layer, wherein the tuning layer controls the microstructure of the interface layer;

depositing a high k dielectric layer over the interface layer, wherein the high k dielectric layer has a thickness of about 80 angstroms to about 800 angstroms; and

depositing an upper electrode layer over the dielectric layer.

20. The method of claim 19, wherein the tuning layer comprises ruthenium oxide, ruthenium combined with ruthenium oxide, iridium oxide, iridium combined with iridium oxide, titanium aluminum nitride and combinations thereof.

21. The method of claim 19, wherein the interface layer comprises platinum, ruthenium, iridium, rhodium, and combinations thereof.

22. The method of claim 19, wherein the bottom layer comprises titanium, titanium nitride, titanium aluminum nitride, tantalum, tantalum nitride, tantalum aluminum nitride, and combinations thereof.

23. The method of claim 19, wherein the bottom layer is titanium.

24. The method of claim 19, wherein the bottom layer has a thickness of about 50 angstroms to about 500 angstroms.

25. The method of claim 19, wherein the barrier layer comprises titanium, titanium nitride, titanium aluminum nitride, tantalum, tantalum nitride, tantalum aluminum nitride, and combinations thereof.

26. The method of claim 19, wherein the barrier layer is titanium aluminum nitride.

27. The method of claim 19, wherein the barrier layer has a thickness of about 50 angstroms to about 500 angstroms.

28. The method of claim 19, wherein the tuning layer has a thickness of about 50 angstroms to about 1,000 angstroms.

29. The method of claim 19, wherein the interface layer is a combination material comprising platinum combined with rhodium, platinum combined with iridium, platinum combined with ruthenium, and combinations thereof.

30. The method of claim 29, wherein the combination material comprises about 75% to about 90% platinum.

31. The method of claim 19, wherein the interface layer has a thickness of about 200 angstroms to about 4,000 angstroms.

32. The method of claim 19, wherein the high k dielectric layer comprises barium strontium titanate, lead zirconate titanate, lead lanthanium titanate, barium titanate, strontium titanate, and strontium bismuth titanate.

33. The method of claim 32, wherein the high k dielectric layer is doped.

34. The method of claim 19, wherein the high k dielectric layer has a thickness of about 200 angstroms to about 300 angstroms.

35. The method of claim 19, wherein the upper electrode layer comprises platinum, ruthenium, iridium, rhodium, platinum combined with rhodium, platinum combined with iridium, platinum combined with ruthenium, and combinations thereof.

36. The method of claim 19, wherein the upper electrode layer has a thickness of about 200 angstroms to about 4,000 angstroms.

37. The method of claim 19, wherein the high k dielectric layer has a median grain thickness of less than 150 angstroms.