Device improvement by lowering LDD resistance with new spacer/silicide process

• US 6,358,826 B1
• Filed: 04/19/2001
• Issued: 03/19/2002
• Est. Priority Date: 06/02/1999
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Horstmann, Manfred, Wieczorek, Karsten, Hause, Frederick N.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Vu, David
• Application Number:
  US09/838,389
• Time in Patent Office: 334 Days
• Field of Search: 438/296, 438/583, 438/301, 438/303, 438/305, 438/306, 438/595, 438/740, 438/664, 257/382-384, 257/769, 257/770, 257/344, 257/336, 257/408
• US Class Current: 438/583
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method is provided for fabricating a semiconductor device on a structure, the method including forming a dielectric layer adjacent a gate conductor of the semiconductor device and above an LDD region of the structure and forming a first dielectric spacer adjacent a first portion of the dielectric layer adjacent the gate conductor and above a second portion of the dielectric layer above the LDD region. The method also includes introducing a dopant into a source/drain region of the structure and removing a third portion of the dielectric layer above the gate conductor, the second portion of the dielectric layer above the LDD region, and the first dielectric spacer. In addition, the method includes forming a first conductive layer above the gate conductor, adjacent the first portion of the dielectric layer and above the LDD region, and saliciding the first conductive layer above the gate conductor and above the LDD region to form a salicided first conductive layer.

Claims

1. A method for fabricating a semiconductor device on a structure, the method comprising:

forming a dielectric layer adjacent a gate conductor of the semiconductor device and above an LDD region of the structure;

forming a first dielectric spacer adjacent a first portion of the dielectric layer adjacent the gate conductor and above a second portion of the dielectric layer above the LDD region;

introducing a dopant into a source/drain region of the structure;

removing a third portion of the dielectric layer above the gate conductor, the second portion of the dielectric layer above the LDD region, and the first dielectric spacer;

forming a first conductive layer above the gate conductor, adjacent the first portion of the dielectric layer and above the LDD region; and

saliciding the first conductive layer above the gate conductor and above the LDD region to form a salicided first conductive layer.

2. The method of claim 1, the method further comprising:

forming a second dielectric spacer adjacent the first portion of the dielectric layer and above a portion of the salicided first conductive layer above the LDD region;

forming a second conductive layer adjacent the second dielectric spacer and above the salicided first conductive layer above the gate conductor and above the source/drain region; and

saliciding the second conductive layer above the gate conductor and above the source/drain region to form a salicided second conductive layer.

3. The method of claim 2, wherein forming the first conductive layer includes forming the first conductive layer from one of titanium, tantalum, nickel, zirconium, tungsten, molybdenum and cobalt and wherein forming the second conductive layer includes forming the second conductive layer from one of titanium, tantalum, nickel, zirconium, tungsten, molybdenum and cobalt.

4. The method of claim 1, wherein forming the dielectric layer includes forming the dielectric layer from one of an oxide and an oxynitride.

5. The method of claim 2, wherein forming the first dielectric spacer includes forming the first dielectric spacer from one of an oxide, a nitride and an oxynitride to have a first base thickness and wherein forming the second dielectric spacer includes forming the second dielectric spacer to have a second base thickness at least as large as the first base thickness.

6. A method for fabricating a MOSFET on a substrate, the method comprising:

forming a dielectric layer adjacent a gate conductor of the MOSFET and above LDD regions of the substrate;

forming first dielectric spacers adjacent a first portion of the dielectric layer adjacent the gate conductor and above a second portion of the dielectric layer above the LDD regions;

introducing a dopant into source/drain regions of the substrate;

removing a third portion of the dielectric layer above the gate conductor, the second portion of the dielectric layer above the LDD regions, and the first dielectric spacers;

forming a first conductive layer above the gate conductor, adjacent the first portion of the dielectric layer and above the LDD regions;

saliciding the first conductive layer above the gate conductor and above the LDD regions to form a salicided first conductive layer;

forming second dielectric spacers adjacent the first portion of the dielectric layer and above a portion of the salicided first conductive layer above the LDD regions;

forming a second conductive layer adjacent the second dielectric spacers and above the salicided first conductive layer above the gate conductor and above the source/drain regions; and

saliciding the second conductive layer above the gate conductor and above the source/drain regions to form a salicided second conductive layer.

7. The method of claim 6, wherein forming the first conductive layer includes forming the first conductive layer from one of titanium, tantalum, nickel, zirconium, tungsten, molybdenum and cobalt.

8. The method of claim 6, wherein forming the second conductive layer includes forming the second conductive layer from one of titanium, tantalum, nickel, zirconium, tungsten, molybdenum and cobalt.

9. The method of claim 6, wherein forming the dielectric layer includes forming the dielectric layer from one of an oxide and an oxynitride.

10. The method of claim 6, wherein forming the first dielectric spacers includes forming the first dielectric spacers from one of an oxide, a nitride and an oxynitride to have a first base thickness and wherein forming the second dielectric spacers includes forming the second dielectric spacers to have a second base thickness at least as large as the first base thickness.

11. A method for fabricating a MOSFET on a substrate, the method comprising:

depositing a dielectric layer adjacent a gate conductor of the MOSFET and above LDD regions of the substrate;

forming first dielectric spacers adjacent a first portion of the dielectric layer adjacent the gate conductor and above a second portion of the dielectric layer above the LDD regions;

implanting a dopant into source/drain regions of the substrate;

etching away a third portion of the dielectric layer above the gate conductor, the second portion of the dielectric layer above the LDD regions, and the first dielectric spacers;

depositing a first conductive layer above the gate conductor, adjacent the first portion of the dielectric layer and above the LDD regions;

annealing the first conductive layer above the gate conductor and above the LDD regions to form a salicided first conductive layer;

forming second dielectric spacers adjacent the first portion of the dielectric layer and above a portion of the salicided first conductive layer above the LDD regions;

depositing a second conductive layer adjacent the second dielectric spacers and above the salicided first conductive layer above the gate conductor and above the source/drain regions; and

annealing the second conductive layer above the gate conductor and above the source/drain regions to form a salicided second conductive layer.

12. The method of claim 11, wherein depositing the first conductive layer includes depositing one of titanium, tantalum, nickel, zirconium, tungsten, molybdenum and cobalt.

13. The method of claim 11, wherein depositing the second conductive layer includes depositing one of titanium, tantalum, nickel, zirconium, tungsten, molybdenum and cobalt.

14. The method of claim 11, wherein depositing the dielectric layer includes depositing one of an oxide and an oxynitride.

15. The method of claim 11, wherein forming the first dielectric spacers includes forming the first dielectric spacers from one of an oxide, a nitride and an oxynitride to have a first base thickness and wherein forming the second dielectric spacers includes forming the second dielectric spacers to have a second base thickness at least as large as the first base thickness.

16. A method for fabricating a MOSFET on a substrate, the method comprising:

depositing a dielectric layer adjacent a gate conductor of the MOSFET and above LDD regions of the substrate, the dielectric layer having a thickness in a range of about 50 Å

-300 Å and

the LDD regions having been implanted with an LDD dose of one of arsenic and boron difluoride and subjected to a rapid thermal anneal process performed at a temperature ranging from approximately 800-1100°

C. for a time ranging from approximately 5-60 seconds, the LDD dose ranging from about 1.0×

10¹⁴-1,0×

10¹⁵ ions/cm² at an implant energy ranging from about 3-50 keV;

forming first dielectric spacers adjacent a first portion of the dielectric layer adjacent the gate conductor and above a second portion of the dielectric layer above the LDD regions, the first dielectric spacers having a first base thickness in a range of about 300 Å

-1500 Å

;

implanting one of phosphorus and boron into source/drain regions of the substrate, a dose of the one of phosphorus and boron ranging from about 1.0×

10¹⁵-5.0×

10¹⁵ ions/cm² at an implant energy ranging from about 30-100 keV;

etching away a third portion of the dielectric layer above the gate conductor, the second portion of the dielectric layer above the LDD regions, and the first dielectric spacers using anisotropic reactive ion etching;

depositing a first conductive layer above the gate conductor, adjacent the first portion of the dielectric layer and above the LDD regions, the first conductive layer having a thickness in a range of about 50 Å

-150 Å

;

annealing the first conductive layer above the gate conductor and above the LDD regions to form a salicided first conductive layer, the first conductive layer being subjected to a rapid thermal anneal process performed at a temperature ranging from approximately 450-800°

C. for a time ranging from approximately 15-60 seconds, a distance between the salicided first conductive layer and a junction between the LDD regions and the substrate being in a range of at least about 50 Å

-200 Å

;

forming second dielectric spacers adjacent the first portion of the dielectric layer and above a portion of the salicided first conductive layer above the LDD regions, the second dielectric spacers having a second base thickness in a range of about 300 Å

-2000 Å

;

depositing a second conductive layer adjacent the second dielectric spacers and above the salicided first conductive layer above the gate conductor and above the source/drain regions, the second conductive layer having a thickness in a range of about 100 Å

-600 Å

; and

annealing the second conductive layer above the gate conductor and above the source/drain regions to form a salicided second conductive layer, the second conductive layer being subjected to an initial rapid thermal anneal process performed at a temperature ranging from approximately 450-800°

C. for a time ranging from approximately 15-60 seconds, the second conductive layer being subjected to wet chemical strip to remove unsilicided portions of the second conductive layer, the second conductive layer being subjected to a final rapid thermal anneal process performed at a temperature ranging from approximately 800-1000°

C. for a time ranging from approximately 10-60 seconds, a distance between the salicided second conductive layer and a junction between the source/drain regions and the substrate being in a range of at least about 50 Å

-200 Å

.

17. The method of claim 16, wherein implanting the one of phosphorus and boron into source/drain regions of the substrate includes subjecting the source/drain regions to a rapid thermal anneal process performed at a temperature ranging from approximately 800-1100°

C. for a time ranging from approximately 5-60 seconds.

18. The method of claim 16, wherein depositing the first conductive layer includes depositing one of titanium, tantalum, nickel, zirconium, tungsten, molybdenum and cobalt and depositing the second conductive layer includes depositing one of titanium, tantalum, nickel, zirconium, tungsten, molybdenum and cobalt.

19. The method of claim 16, wherein depositing the dielectric layer includes depositing one of an oxide and an oxynitride.

20. The method of claim 16, wherein forming the first dielectric spacers includes forming the first dielectric spacers from one of an oxide, a nitride and an oxynitride and wherein forming the second dielectric spacers includes forming the second dielectric spacers to have the second base thickness at least as large as the first base thickness.

21. A MOSFET on a substrate formed by a method comprising:

depositing a dielectric layer adjacent a gate conductor of the MOSFET and above LDD regions of the substrate;

forming first dielectric spacers adjacent a first portion of the dielectric layer adjacent the gate conductor and above a second portion of the dielectric layer above the LDD regions;

implanting a dopant into source/drain regions of the substrate;

etching away a third portion of the dielectric layer above the gate conductor, the second portion of the dielectric layer above the LDD regions, and the first dielectric spacers;

depositing a first conductive layer above the gate conductor, adjacent the first portion of the dielectric layer and above the LDD regions;

annealing the first conductive layer above the gate conductor and above the LDD regions to form a salicided first conductive layer;

forming second dielectric spacers adjacent the first portion of the dielectric layer and above a portion of the salicided first conductive layer above the LDD regions;

depositing a second conductive layer adjacent the second dielectric spacers and above the salicided first conductive layer above the gate conductor and above the source/drain regions; and

annealing the second conductive layer above the gate conductor and above the source/drain regions to form a salicided second conductive layer.

22. The MOSFET of claim 21, wherein depositing the first conductive layer includes depositing one of titanium, tantalum, nickel, zirconium, tungsten, molybdenum and cobalt.

23. The MOSFET of claim 21, wherein depositing the second conductive layer includes depositing one of titanium, tantalum, nickel, zirconium, tungsten, molybdenum and cobalt.

24. The MOSFET of claim 21, wherein depositing the dielectric layer includes depositing one of an oxide and an oxynitride.

25. The MOSFET of claim 21, wherein forming the first dielectric spacer includes forming the first dielectric spacer from one of an oxide, a nitride and an oxynitride to have a first base thickness and wherein forming the second dielectric spacer includes forming the second dielectric spacer to have a second base thickness at least as large as the first base thickness.

26. A MOSFET on a substrate formed by a method comprising:

depositing a dielectric layer adjacent a gate conductor of the MOSFET and above LDD regions of the substrate, the dielectric layer having a thickness in a range of about 50 Å

-300 Å and

the LDD regions having been implanted with an LDD dose of one of arsenic and boron difluoride and subjected to a rapid thermal anneal process performed at a temperature ranging from approximately 800-1100°

C. for a time ranging from approximately 5-60 seconds, the LDD dose ranging from about 1.0×

10¹⁴-1.0×

10¹⁵ ions/cm² at an implant energy ranging from about 3-50 keV;

forming first dielectric spacers adjacent a first portion of the dielectric layer adjacent the gate conductor and above a second portion of the dielectric layer above the LDD regions, the first dielectric spacers having a first base thickness in a range of about 300 Å

-1500 Å

;

implanting one of phosphorus and boron into source/drain regions of the substrate, a dose of the one of phosphorus and boron ranging from about 1.0×

10¹⁵-5.0×

10¹⁵ ions/cm² at an implant energy ranging from about 30-100 keV;

etching away a third portion of the dielectric layer above the gate conductor, the second portion of the dielectric layer above the LDD regions, and the first dielectric spacers using anisotropic reactive ion etching;

depositing a first conductive layer above the gate conductor, adjacent the first portion of the dielectric layer and above the LDD regions, the first conductive layer having a thickness in a range of about 50 Å

-150 Å

;

annealing the first conductive layer above the gate conductor and above the LDD regions to form a salicided first conductive layer, the first conductive layer being subjected to a rapid thermal anneal process performed at a temperature ranging from approximately 450-800°

C. for a time ranging from approximately 15-60 seconds, a distance between the salicided first conductive layer and a junction between the LDD regions and the substrate being in a range of at least about 50 Å

-200 Å

;

forming second dielectric spacers adjacent the first portion of the dielectric layer and above a portion of the salicided first conductive layer above the LDD regions, the second dielectric spacers having a second base thickness in a range of about 300 Å

-2000 Å

;

depositing a second conductive layer adjacent the second dielectric spacers and above the salicided first conductive layer above the gate conductor and above the source/drain regions, the second conductive layer having a thickness in a range of about 100 Å

-600 Å

; and

annealing the second conductive layer above the gate conductor and above the source/drain regions to form a salicided second conductive layer, the second conductive layer being subjected to an initial rapid thermal anneal process performed at a temperature ranging from approximately 450-800°

C. for a time ranging from approximately 15-60 seconds, the second conductive layer being subjected to wet chemical strip to remove unsilicided portions of the second conductive layer, the second conductive layer being subjected to a final rapid thermal anneal process performed at a temperature ranging from approximately 800-1000°

C. for a time ranging from approximately 10-60 seconds, a distance between the salicided second conductive layer and a junction between the source/drain regions and the substrate being in a range of at least about 50 Å

-200 Å

.

27. The MOSFET of claim 26, wherein implanting the one of phosphorus and boron into source/drain regions of the substrate includes subjecting the source/drain regions to a rapid thermal anneal process performed at a temperature ranging from approximately 800-1100°

C. for a time ranging from approximately 5-60 seconds.

28. The MOSFET of claim 26, wherein depositing the first conductive layer includes depositing one of titanium, tantalum, nickel, zirconium, tungsten, molybdenum and cobalt and depositing the second conductive layer includes depositing one of titanium, tantalum, nickel, zirconium, tungsten, molybdenum and cobalt.

29. The MOSFET of claim 26, wherein depositing the dielectric layer includes depositing one of an oxide and an oxynitride.

30. The MOSFET of claim 26, wherein forming the first dielectric spacer includes forming the first dielectric spacer from one of an oxide, a nitride and an oxynitride and wherein forming the second dielectric spacers includes forming the second dielectric spacers to have the second base thickness at least as large as the first base thickness.