Method of reducing electromigration in copper lines by forming an interim layer of calcium-doped copper seed layer in a chemical solution and semiconductor device thereby formed

• US 6,358,848 B1
• Filed: 11/30/2000
• Issued: 03/19/2002
• Est. Priority Date: 11/30/2000
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Lopatin, Sergey
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Pham, Thanhha
• Application Number:
  US09/728,685
• Time in Patent Office: 474 Days
• Field of Search: 438/687, 438/660, 438/663, 438/667, 438/668, 438/674, 438/675, 438/678, 438/622, 438/620, 438/625, 438/626, 438/627, 438/628, 438/629, 438/631-633, 438/642, 438/652-654
• US Class Current: 438/687
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76858 by diffusing alloying elements
• CPC Class Codes: H01L 21/76862 Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 2221/1089 Stacks of seed layers
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of reducing electromigration in Cu interconnect lines by forming an interim layer of Ca-doped copper seed layer lining a via in a chemical solution and a semi conductor device thereby formed. The method reduces the drift velocity which then decreases the Cu migration rate in addition to void formation rate. The method comprises: depositing a Cu seed layer in the via; treating the Cu seed layer in a chemical solution, selectively forming a Cu—Ca—X conformal layer on the Cu seed layer, wherein X denotes at least one contaminant; and processing the Cu—Ca—X conformal layer, effecting a thin Cu—Ca conformal layer on the Cu seed layer; annealing the thin Cu—Ca conformal layer onto the Cu seed layer, removing the at least one contaminant, thereby forming a contaminant-reduced Cu—Ca alloy surface on the Cu seed layer; electroplating the contaminant-reduced Cu—Ca alloy surface with Cu, thereby forming a contaminant-reduced Cu—Ca/Cu interconnect structure; annealing the at least one contaminant-reduced Cu—Ca/Cu interconnect structure, thereby forming at least one virtually void-less and contaminant-reduced Cu—Ca/Cu interconnect structure; and chemical mechanical polishing the at least one virtually void-less and contaminant-reduced Cu—Ca/Cu interconnect structure.

Claims

1. A method of fabricating a semiconductor device having a virtually voidless and contaminant-reduced copper-calcium alloy surface on copper (Cu—

Ca/Cu) interconnect structure for reducing electromigration therein, comprising;

A. providing a semiconductor substrate, the substrate having at least one via formed therein;

B. depositing a copper (Cu) seed layer in the at least one via for facilitating subsequent formation of at least one Cu interconnect line, the Cu seed layer lining the at least one via, the Cu seed layer comprising at least one intermediate Cu layer selected from a group of intermediate copper layers consisting essentially of;

(1) a blanket Cu seed layer, and

(2) a partial thickness Cu plated layer;

C. treating the Cu seed layer in a chemical solution, thereby selectively forming a copper-calcium-X (Cu—

Ca—

X) conformal layer on the Cu seed layer, wherein X denotes at least one contaminant;

D. processing the Cu—

Ca—

X conformal layer by a technique selected from a group of techniques consisting essentially of;

(1) proceeding to step (E),

(2) sputtering under an argon (Ar) atmosphere, and

(3) treating in a plasma ambient;

E. annealing the Cu—

Ca—

X conformal layer,

thereby removing the at least one contaminant,

thereby decreasing thickness of the Cu—

Ca—

X conformal layer,

thereby forming a thin Cu—

Ca conformal layer on the Cu seed layer,

whereby the thin Cu—

Ca conformal layer is alloyed, and

thereby forming a contaminant-reduced Cu—

Ca alloy surface on the Cu seed layer;

F. electroplating the contaminant-reduced Cu—

Ca alloy surface with Cu for filling the volume of the at least one via,

thereby forming the at least one Cu interconnect line, and

thereby forming at least one contaminant-reduced Cu—

Ca/Cu interconnect structure in the via;

G. annealing the at least one containment-reduced Cu—

Ca/Cu interconnect structure,

thereby forming at least one virtually voidless and contaminant-reduced Cu—

Ca/Cu interconnect structure;

H. chemical-mechanical-polishing the at least one virtually voidless and contaminant-reduced Cu—

Ca/Cu interconnect structure for forming a planarized surface; and

I. completing formation of the semiconductor device.

2. A method, as recited in claim 1,

wherein the chemical solution comprises an electroless plating solution, and

wherein the electroless plating solution comprises:

a. at least one solvent,

b. at least one Cu salt;

C. at least one Ca salt;

d. at least one complexing agent; and

e. at least one reducing agent, (b) through (e) being dissolved in (a).

3. A method, as recited in claim 2, wherein the electroless plating solution further comprises:

f. at least one pH adjuster; and

g. at least one surfactant, (f) and (g) being dissolved in (a).

4. A method, as recited in claim 1, wherein the at least one contaminant is selected from a group of contaminants consisting essentially of carbon (C), sulphur (S), and oxygen (O).

5. A method, as recited in claim 1, wherein the annealing step (E) is performed in a temperature range of 250°

C. to 450°

C. and in an environment selected from a group of environments consisting essentially of a vacuum, an inert gas, and a reducing ambient.

6. A method, as recited in claim 1, wherein the Cu—

Ca alloy surface is Cu-rich with a Ca-doping level in a concentration range of 0.2 atomic % to 5 atomic %.

7. A method, as recited in claim 2, wherein the Cu—

Ca alloy surface is Cu-rich with a Ca-doping level in a concentration range of 0.2 atomic % to 5 atomic %.

8. A method, as recited in claim 3, wherein the Cu—

Ca alloy surface is Cu-rich with a Ca-doping level in a concentration range of 0.2 atomic % to 5 atomic %.

9. A method, as recited in claim 1, further comprising a barrier layer formed in each at least one via.

10. A method, as recited in claim 9,

wherein the barrier layer comprises tantalum (Ta),

wherein the blanket Cu seed layer is deposited by a technique selected from a group of techniques consisting essentially of electroplating, electroless plating, chemical vapor deposition (CVD), plasma vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD),

wherein the partial thickness Cu plated layer is deposited by a technique comprising electroplating, and

wherein the Cu interconnect line is dual inlaid.

11. A method of fabricating a semiconductor device having a virtually void-less and contaminant-reduced copper-calcium alloy surface on copper (Cu—

Ca/Cu) interconnect structure for reducing electromigration therein, as recited in claim 9,

wherein the barrier layer comprises tantalum (Ta),

wherein the blanket Cu seed layer is deposited by a technique selected from a group of techniques consisting essentially of electroplating, electroless plating, chemical vapor deposition (CVD), plasma vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD),

wherein the partial thickness Cu plated layer is deposited by a technique comprising electroplating, and

wherein the Cu interconnect line is dual inlaid,

wherein the chemical solution comprises an electroless plating solution,

wherein the electroless plating solution comprises;

a. at least one solvent;

b. at least one Cu salt,

C. at least one Ca salt,

d. at least one complexing agent,

e. at least one reducing agent,

f. at least one pH adjuster, and

g. at least one surfactant, (b) through (g) being dissolved in (a),

wherein the at least one contaminant is selected from a group of contaminants consisting essentially of carbon (C), sulphur (S), and oxygen (O),

wherein the annealing step (E) is performed in a temperature range of 250°

C. to 450°

C. in an environment selected from a group of environments consisting essentially of a vacuum, an inert gas, and a reducing ambient, and

wherein the contaminant-reduced Cu—

Ca alloy surface is Cu-rich with a Ca-doping level in a concentration range of 0.2 atomic % to 5 atomic %.