Passivation integrity improvements

• US 6,358,862 B1
• Filed: 09/02/1999
• Issued: 03/19/2002
• Est. Priority Date: 09/02/1999
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Green, James E., Ireland, Philip J.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Luk, Olivia T.
• Application Number:
  US09/389,658
• Time in Patent Office: 929 Days
• Field of Search: 438/758, 438/688, 438/622, 438/720, 438/619, 438/72, 257/635, 257/530
• US Class Current: 438/758
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/19041 being a capacitor

Abstract

An exemplary implementation of the invention is a process for forming passivation protection on a semiconductor assembly by the steps of: forming a layer of oxide over patterned metal lines having sidewalls; forming a first passivation layer of silicon nitride over the layer of oxide such that the first passivation layer of silicon nitride resides along the sidewalls of metal lines and pinches off a gap between the metal lines; performing a facet etch to remove material from the edges of the first passivation layer of silicon nitride and re-deposits some of removed material across a pinch-off junction; forming a second passivation layer of silicon nitride on the first passivation layer of silicon nitride.

Claims

1. A process for forming passivation protection on a semiconductor assembly, said process comprising the steps of:

forming a layer of oxide over patterned metal lines having sidewalls;

forming a passivation layer of silicon nitride on said layer of oxide such that said passivation layer of silicon nitride resides along said sidewalls of said metal lines and pinches off a gap between said metal lines.

2. The process as recited in claim 1, wherein said step of forming a passivation layer of silicon nitride comprises depositing silicon nitride by plasma enhanced chemical vapor deposition at a deposition temperature that is less than the melting point of said patterned metal lines.

3. The process as recited in claim 1, wherein said gap between said metal lines comprises an air gap.

4. A process for forming passivation protection on a semiconductor assembly, said process comprising the steps of:

forming a layer of oxide over patterned metal lines having sidewalls, said layer of oxide having bread-loafed corners;

forming a first passivation layer of silicon nitride on said layer of oxide such that said first passivation layer of silicon nitride resides along said sidewalls of said metal lines and pinches off a gap between said metal lines at a pinch-off junction;

performing a facet etch to remove material from the edges of said first passivation layer of silicon nitride and re-depositing some of said material across said pinch-off junction;

forming a second passivation layer of silicon nitride on said first passivation layer of silicon nitride.

5. The process as recited in claim 4, wherein said steps of forming first and second passivation layers of silicon nitride comprise depositing silicon nitride by plasma enhanced chemical vapor deposition at a deposition temperature that is less than the melting point of said patterned metal lines.

6. The process as recited in claim 4, wherein said gap between said metal lines comprises an air gap.

7. A process for forming passivation protection on a semiconductor assembly, said process comprising the steps of:

forming a layer of oxide over patterned metal lines having sidewalls, said layer of oxide having bread-loafed corners;

forming a first passivation layer of silicon nitride on said layer of oxide such that said first passivation layer of silicon nitride resides along said sidewalls of said metal lines and pinches off a gap between said metal lines at a pinch-offjunction;

performing a facet etch to remove material from the edges of said first passivation layer of silicon nitride and re-depositing some of said material across said pinch-off junction until a non-disjointed contour of said first passivation layer of silicon nitride is formed;

forming a second passivation layer of silicon nitride on said first passivation layer of silicon nitride.

8. The process as recited in claim 7, wherein said steps of forming first and second passivation layers of silicon nitride comprise depositing silicon nitride by plasma enhanced chemical vapor deposition at a deposition temperature that is less than the melting point of said patterned metal lines.

9. The process as recited in claim 7, wherein said gap between said metal lines comprises an air gap.

10. A process for forming a mobile ion barrier on a semiconductor assembly, said process comprising the steps of:

forming a layer of oxide over patterned metal lines having sidewalls;

forming a passivation layer of silicon nitride on said layer of oxide such that said passivation layer of silicon nitride resides along said sidewalls of said metal lines and pinches off a gap between said metal lines.

11. The process as recited in claim 10, wherein said step of forming a passivation layer of silicon nitride comprises depositing silicon nitride by plasma enhanced chemical vapor deposition at a deposition temperature that is less than the melting point of said patterned metal lines.

12. The process as recited in claim 10, wherein said gap between said metal lines comprises an air gap.

13. A process for forming a mobile ion barrier on a semiconductor assembly, said process comprising the steps of:

forming a layer of oxide over patterned metal lines having sidewalls, said layer of oxide having bread-loafed corners;

forming a first passivation layer of silicon nitride on said layer of oxide such that said first passivation layer of silicon nitride resides along said sidewalls of said metal lines and pinches off a gap between said metal lines at a pinch-offjunction;

performing a facet etch to remove material from the edges of said first passivation layer of silicon nitride and re-depositing some of said material across said pinch-off junction until a non-disjointed contour of said first passivation layer of silicon nitride is formed;

forming a second passivation layer of silicon nitride on said first passivation layer of silicon nitride.

14. The process as recited in claim 13, wherein said steps of forming first and second passivation layers of silicon nitride comprise depositing silicon nitride by plasma enhanced chemical vapor deposition at a deposition temperature that is less than the melting point of said patterned metal lines.

15. The process as recited in claim 13, wherein said gap between said metal lines comprises an air gap.

16. A process for forming passivation protection on a semiconductor assembly, said process comprising the steps of:

forming a layer of oxide over patterned metal lines having sidewalls such that said forming of said layer of oxide avoids pinching off a gap between said sidewalls of said patterned metal lines;

forming a passivation layer of silicon nitride on said layer of oxide such that said passivation layer of silicon nitride resides along said sidewalls of said patterned lines and pinches off a gap therebetween.

17. The process as recited in claim 16, wherein said step of forming a passivation layer of silicon nitride comprises depositing silicon nitride by plasma enhanced chemical vapor deposition at deposition temperature that is less than melting point of said patterned metal lines.

18. The process as in claim 16, wherein said gap between said patterned metal lines comprises an air gap.

19. A process for forming a mobile ion barrier on a semiconductor assembly, said process comprising the steps of:

forming a layer of oxide over patterned metal lines having sidewalls such that said forming of said layer of oxide avoids pinching off a gap between said sidewalls of said patterned metal lines;

forming a passivation layer of silicon nitride on said layer of oxide such that said passivation layer of silicon nitride resides along said sidewalls of said patterned metal lines and pinches off a gap therebetween.

20. The process as recited in claim 19, wherein said step of forming a passivation layer of silicon nitride comprises depositing silicon nitride by plasma enhanced chemical vapor deposition at a deposition temperature that is less than the melting point of said patterned metal lines.

21. The process as recited in claim 19, wherein said gap between said metal lines comprises an air gap.