Passivation integrity improvements
First Claim
1. A process for forming passivation protection on a semiconductor assembly, said process comprising the steps of:
- forming a layer of oxide over patterned metal lines having sidewalls;
forming a passivation layer of silicon nitride on said layer of oxide such that said passivation layer of silicon nitride resides along said sidewalls of said metal lines and pinches off a gap between said metal lines.
1 Assignment
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Accused Products
Abstract
An exemplary implementation of the invention is a process for forming passivation protection on a semiconductor assembly by the steps of: forming a layer of oxide over patterned metal lines having sidewalls; forming a first passivation layer of silicon nitride over the layer of oxide such that the first passivation layer of silicon nitride resides along the sidewalls of metal lines and pinches off a gap between the metal lines; performing a facet etch to remove material from the edges of the first passivation layer of silicon nitride and re-deposits some of removed material across a pinch-off junction; forming a second passivation layer of silicon nitride on the first passivation layer of silicon nitride.
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Citations
21 Claims
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1. A process for forming passivation protection on a semiconductor assembly, said process comprising the steps of:
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forming a layer of oxide over patterned metal lines having sidewalls;
forming a passivation layer of silicon nitride on said layer of oxide such that said passivation layer of silicon nitride resides along said sidewalls of said metal lines and pinches off a gap between said metal lines. - View Dependent Claims (2, 3)
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4. A process for forming passivation protection on a semiconductor assembly, said process comprising the steps of:
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forming a layer of oxide over patterned metal lines having sidewalls, said layer of oxide having bread-loafed corners;
forming a first passivation layer of silicon nitride on said layer of oxide such that said first passivation layer of silicon nitride resides along said sidewalls of said metal lines and pinches off a gap between said metal lines at a pinch-off junction;
performing a facet etch to remove material from the edges of said first passivation layer of silicon nitride and re-depositing some of said material across said pinch-off junction;
forming a second passivation layer of silicon nitride on said first passivation layer of silicon nitride. - View Dependent Claims (5, 6)
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7. A process for forming passivation protection on a semiconductor assembly, said process comprising the steps of:
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forming a layer of oxide over patterned metal lines having sidewalls, said layer of oxide having bread-loafed corners;
forming a first passivation layer of silicon nitride on said layer of oxide such that said first passivation layer of silicon nitride resides along said sidewalls of said metal lines and pinches off a gap between said metal lines at a pinch-offjunction;
performing a facet etch to remove material from the edges of said first passivation layer of silicon nitride and re-depositing some of said material across said pinch-off junction until a non-disjointed contour of said first passivation layer of silicon nitride is formed;
forming a second passivation layer of silicon nitride on said first passivation layer of silicon nitride. - View Dependent Claims (8, 9)
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10. A process for forming a mobile ion barrier on a semiconductor assembly, said process comprising the steps of:
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forming a layer of oxide over patterned metal lines having sidewalls;
forming a passivation layer of silicon nitride on said layer of oxide such that said passivation layer of silicon nitride resides along said sidewalls of said metal lines and pinches off a gap between said metal lines. - View Dependent Claims (11, 12)
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13. A process for forming a mobile ion barrier on a semiconductor assembly, said process comprising the steps of:
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forming a layer of oxide over patterned metal lines having sidewalls, said layer of oxide having bread-loafed corners;
forming a first passivation layer of silicon nitride on said layer of oxide such that said first passivation layer of silicon nitride resides along said sidewalls of said metal lines and pinches off a gap between said metal lines at a pinch-offjunction;
performing a facet etch to remove material from the edges of said first passivation layer of silicon nitride and re-depositing some of said material across said pinch-off junction until a non-disjointed contour of said first passivation layer of silicon nitride is formed;
forming a second passivation layer of silicon nitride on said first passivation layer of silicon nitride. - View Dependent Claims (14, 15)
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16. A process for forming passivation protection on a semiconductor assembly, said process comprising the steps of:
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forming a layer of oxide over patterned metal lines having sidewalls such that said forming of said layer of oxide avoids pinching off a gap between said sidewalls of said patterned metal lines;
forming a passivation layer of silicon nitride on said layer of oxide such that said passivation layer of silicon nitride resides along said sidewalls of said patterned lines and pinches off a gap therebetween. - View Dependent Claims (17, 18)
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19. A process for forming a mobile ion barrier on a semiconductor assembly, said process comprising the steps of:
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forming a layer of oxide over patterned metal lines having sidewalls such that said forming of said layer of oxide avoids pinching off a gap between said sidewalls of said patterned metal lines;
forming a passivation layer of silicon nitride on said layer of oxide such that said passivation layer of silicon nitride resides along said sidewalls of said patterned metal lines and pinches off a gap therebetween. - View Dependent Claims (20, 21)
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Specification