Cellular trench-gate field-effect transistors

• US 6,359,308 B1
• Filed: 07/24/2000
• Issued: 03/19/2002
• Est. Priority Date: 07/22/1999
• Status: Expired due to Term

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Hijzen, Erwin A., Hueting, Raymond J.E.
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): DIAZ, JOSE R
• Application Number:
  US09/624,481
• Time in Patent Office: 603 Days
• Field of Search: 257/327-334, 257/341, 257/488, 257/496
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A cellular trench-gate field-effect transistor comprises a field plate (38) on dielectric material (28) in a perimeter trench (18). The dielectric material (28) forms a thicker dielectric layer than the gate dielectric layer (21) in the array trenches (11). The field plate (38) is connected to the source (3) or trench-gate (31) of the transistor and acts inwardly towards the cellular array rather than outwardly towards the body perimeter (15) because of its presence on the inside wall 18a of the trench (18) without acting on any outside wall (18b). The array and perimeter trenches (11,18) are sufficiently closely spaced, and the intermediate areas (4a, 4b) of the drain drift region (4) are sufficiently lowly doped, that the depletion layer (40) formed in the drain drift region (4) in the blocking state of the transistor depletes the whole of these intermediate areas between neighbouring trenches at a voltage less than the breakdown voltage. This arrangement reduces the risk of premature breakdown that can occur at high field points in the depletion layer (40), especially at the perimeter of the cellular array.

Claims

1. A cellular trench-gate field-effect transistor comprising a semiconductor body having an array of transistor cells, the cells being bounded by a pattern of trenches lined with dielectric material within the array and around the perimeter of the array, the array trenches extending from a surface of semiconductor body through a body region of a first conductivity type into an underlying drain drift region of an opposite second conductivity type, the perimeter trench having an inside wall around the drain drift region of the array, the dielectric material in the array trenches providing a gate dielectric layer adjacent to the body region, a gate electrode on the gate dielectric layer so as to provide a trench-gate in the array trenches for controlling current flow in a conduction channel from a source region at the surface of the body to the drain drift region in a conductive state of the transistor, and a field plate on is dielectric material in the perimeter trench, a depletion layer being formed in the drain drift region of the array from the a p-n junction the body region, from the trench-gate and from the field-plate in a blocking state of the transistor, characterised in that the dielectric material in the perimeter trench forms a thicker dielectric layer than the gate dielectric layer, in that the field plate is connected to one of the source and trench-gate of the transistor and is present on said thicker dielectric layer on said inside wall of the perimeter trench without acting on any outside wall, and in that the array and perimeter trenches are sufficiently closely spaced and the intermediate areas of the drain drift region are sufficiently lowly doped that the depletion layer formed in the drain drift region in the blocking state of the transistor depletes the whole of the intermediate areas of the drain drift region between the trenches at a voltage less than the breakdown voltage.

2. A transistor as claimed in claim 1, further characterised in that the perimeter trench extends deeper in semiconductor body than the array trenches.

3. A transistor as claimed in claim 2, further characterised in that the drain drift region is present on a higher conductivity substrate of the second conductivity type, and the perimeter trench extends through the thickness of the drain drift region to the substrate.

4. A transistor as claimed in claim 1, further characterised in that the perimeter trench is wider than the array trenches.

5. A transistor as claimed in claim 4, further characterised in that the perimeter trench extends to the perimeter of the semiconductor body and so provides no outside wall.

6. A transistor as claimed in claim 1, further characterised in that a portion of the body region is present between the outer cells of the array and the perimeter trench and has a source region at the surface of semiconductor body adjacent to the trench-gate.

7. A transistor as claimed in claim 6, further characterised in that the field plate is connected to the trench-gate, the thicker dielectric in the perimeter trench is thinner adjacent the portion of the body region between the perimeter trench and the outer cells of the array and forms a gate dielectric, and a source region is present at the surface of semiconductor body adjacent to the perimeter trench.

8. A transistor as claimed in claim 1, further characterised in that a region of the first conductivity type is present between at least one outer cell of the array and the perimeter trench and forms the p-n junction with the drain drift region.

9. A transistor as claimed in claim 1, further characterised in that the drain drift region has a doping concentration of the second conductivity type that increases with depth, and the dielectric material in the array trenches adjacent the increased doping concentration of the drain drift region is thicker than the gate dielectric layer.

10. A transistor as claimed in claim 9, further characterised in that the thicker dielectric material in the array trenches is of the same thickness as the thicker dielectric layer in the perimeter trench.