Probe card and test system for semiconductor wafers

• US 6,359,456 B1
• Filed: 08/14/2001
• Issued: 03/19/2002
• Est. Priority Date: 02/11/1997
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren M., Hembree, David R., Wood, Alan G., Akram, Salman, Doherty, C. Patrick, Krivy, Andrew J.
• Primary Examiner(s): KARLSEN, ERNEST F
• Application Number:
  US09/929,388
• Time in Patent Office: 217 Days
• Field of Search: 324/754, 324/755, 324/757, 324/758, 324/761, 324/765, 439/66, 439/67, 439/68
• US Class Current: 324/750.16
• CPC Class Codes: G01R 1/073 Multiple probes
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06

Abstract

A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.

Claims

1. A probe card for testing semiconductor dice contained on a wafer, comprising:

a mounting plate comprising a sealed space;

a substrate slidably mounted to the mounting plate within the sealed space comprising a plurality of patterns of contact members configured to electrically contact a plurality of patterns of contact locations on the dice;

a gas supply in flow communication with the sealed space configured to exert a biasing force on the substrate; and

a membrane bonded to the mounting plate configured to provide electrical paths from a test circuitry to the contact members.

2. The probe card of claim 1 further comprising a leveling mechanism configured to level the substrate with respect to the wafer.

3. The probe card of claim 2 wherein the leveling mechanism comprises leveling screws or shims.

4. The probe card of claim 2 wherein the leveling mechanism includes leveling springs.

5. A system for testing a semiconductor wafer having a plurality of contact locations comprising:

a testing apparatus in electrical communication with a test circuitry configured to apply test signals to the wafer;

a mounting plate on the testing apparatus comprising a plurality of pads and a plurality of internal conductors in electrical communication with the pads;

a substrate on the mounting plate comprising a plurality of contact members in electrical communication with the conductors on the mounting plate configured to electrically contact the contact locations on the wafer;

a compressible member between the mounting plate and the substrate configured to cushion forces applied to the wafer; and

a plurality of electrical connectors on the testing apparatus in electrical communication with the test circuit and in physical and electrical contact with the pads on the mounting plate.

6. The system of claim 5 wherein the electrical connectors comprise spring loaded pins.

7. The system of claim 5 further comprising a plurality of wires bonded to the substrate and to the mounting plate configured to provide electrical paths between the conductors and the contact members.

8. The system of claim 5 wherein the pads are arranged in a grid array.

9. The system of claim 5 wherein the connectors comprise pogo pins.

10. The system of claim 5 wherein each contact member comprises a raised member comprising a surface and a projection on the surface configured to penetrate a contact location on the wafer.

11. The system of claim 5 wherein the mounting substrate comprises ceramic and the conductors are embedded in the ceramic.

12. The system of claim 5 wherein the testing apparatus comprises a wafer prober.

13. A system for testing a semiconductor wafer having a plurality of contact locations comprising:

a testing apparatus comprising a wafer prober;

a test circuit configured to apply test signals to the wafer;

a mounting plate on the testing apparatus comprising a plurality of pads in a grid array and a plurality of internal conductors in electrical communication with the pads;

a substrate on the mounting plate comprising a plurality of contact members in electrical communication with the conductors on the mounting plate configured to electrically contact the contact locations on the wafer; and

a plurality of electrical connectors on the testing apparatus comprising pogo pins in electrical communication with the test circuit, the electrical connectors in physical and electrical contact with the pads on the mounting plate.

14. The system of claim 13 wherein the mounting plate comprises ceramic and the internal conductors are embedded in the ceramic.

15. The system of claim 13 further comprising a compressible member between the mounting plate and the substrate configured to cushion forces applied to the wafer.

16. The system of claim 13 wherein the contact members comprises pins having a spring segment.

17. The system of claim 13 wherein the contact members comprise raised members having projections for penetrating the contact locations.

18. The system of claim 13 wherein the contact locations comprise bumps and the contact members comprise depression in the substrate at least partially covered by conductive layers.

19. A system for testing a semiconductor wafer containing a plurality of semiconductor dice having a plurality of contact locations comprising:

a testing apparatus configured to support the wafer;

a test circuit configured to apply test signals to the wafer;

a mounting plate on the testing apparatus comprising a plurality of pads in a grid array and a plurality of internal conductors in electrical communication with the pads;

a substrate on the mounting plate comprising a plurality of patterns of contact members in electrical communication with the conductors on the mounting plate configured to electrically contact the contact locations on the dice;

a compressible member between the mounting plate and the substrate configured to cushion forces applied by the testing apparatus to the wafer and a plurality of electrical connectors on the testing apparatus comprising pogo pins in electrical communication with the test circuit, the electrical connectors in physical and electrical contact with the pads on the mounting plate.

20. The system of claim 19 wherein the contact members comprises pins having a spring segment.

21. The system of claim 19 wherein the contact members comprise raised members having projections for penetrating the contact locations.

22. The system of claim 19 wherein the contact locations comprise bumps and the contact members comprise depression in the substrate at least partially covered by conductive layers.

23. The system of claim 19 wherein the testing apparatus comprises a wafer prober.

24. The system of claim 19 wherein the mounting plate comprises ceramic and the internal conductors are embedded in the ceramic.

25. The system of claim 19 further comprising a plurality of wires bonded to the substrate and to the mounting plate configured to provide electrical paths between the conductors and the contact members.