Basic cell for programmable analog time-continuous filter

• US 6,359,503 B1
• Filed: 08/12/1997
• Issued: 03/19/2002
• Est. Priority Date: 02/22/1995
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Inventors: Alini, Roberto, Brianti, Francesco, Demicheli, Marco, Pisati, Valerio
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US08/999,962
• Time in Patent Office: 1,680 Days
• Field of Search: 327/277, 327/552, 327/553, 327/555, 327/556, 327/557, 327/558, 327/559, 327/562, 327/563, 327/103, 327/266, 327/287, 330/305, 330/306, 330/252
• US Class Current: 327/552
• CPC Class Codes: H02P 6/21 Open loop start
• CPC Class Codes: H03H 11/0422 using transconductance amplifiers, e.g. gmC filters
• CPC Class Codes: H03H 15/00 Transversal filters electromechanical filters H03H9/46, H03H9/70

Abstract

An elementary cell structure for programmable time-continuous analog filters and in particular for the processing of analog signals in read/write operations on magnetic supports comprises an amplifier stage provided with a pair of structurally identical transconductance half-cells connected together in a common circuit node. With a cascade of cells of this type is provided a time-continuous analog delay line which is used in a transverse time-continuous analog filter. This filter comprises a cascade of identical delay lines connected through multiplier nodes to a final summation node. “Elementary cell structure for programmable time-continuous analog filters and in particular for read/write operations on magnetic supports and associated analog filter”

Claims

1. A cell structure for analog filters comprising:

a differential amplifier stage inserted between a first reference supply voltage and a second reference voltage, said amplifier stage having at least one input terminal and at least one output terminal;

wherein said amplifier stage comprises a pair of structurally identical half-cells, each provided with a transconductance amplifier stage and each having a differential output terminal connected through a respective capacitor to a common circuit node, each half cell comprising;

a first transistor having a control terminal coupled to a differential input terminal of the amplifier stage, a first conduction terminal coupled to a high reference voltage source and a second conduction terminal, the first conduction terminal being unconnected to the other half cell;

a second transistor having a control terminal, a first conduction terminal coupled thereto so as to form a diode-connected transistor, and a second conduction terminal coupled to the second conduction terminal of the first transistor, the output terminal appearing at the first conduction terminal of the second transistor;

a first current source providing a current to the first conduction terminal of the second transistor; and

a second current source sinking a current from the second terminal of the first and second transistors.

2. The cell structure for analog filters of claim 1 characterized in that each half-cell comprises at least one pair of bipolar transistors.

3. The cell structure for analog filters of claim 1 characterized in that each half-cell comprises at least one pair of field-effect transistors.

4. The cell structure of claim 1, wherein said amplifier stage has no negative feedback.

5. The cell structure of claim 1, wherein each half cell further comprises:

a third transistor having a control terminal coupled to the first conduction terminal of the first transistor, a first conduction terminal coupled to the first conduction terminal of the second transistor, and a second conduction terminal coupled to a second common circuit node; and

a fourth transistor having a control terminal coupled to a bias voltage, a first conduction terminal coupled to the high reference voltage source and a second conduction terminal coupled to the first conduction terminal of the first transistor.

6. The cell structure of claim 1, further comprising:

an output stage connected in cascade relation to the amplifier stage, the output stage comprising a pair of structurally identical half output stages connected through a respective second capacitor to a second common circuit node, the output terminals of the amplifier stage provided to input terminals of the output stage.

7. The cell structure of claim 6, wherein each half output stage comprises a differential amplifier circuit.

8. A time-continuous analog delay line comprising:

a cascade of cells, each cell having a fully differential amplifier stage inserted between a first reference supply voltage and a second reference voltage, said amplifier stage having at least one input terminal and at least one output terminal;

wherein said amplifier stage comprises a pair of structurally identical half-cells, each provided with a transconductance amplifier stage and each connected through a respective capacitor to a common circuit node, each half cell comprising;

a first transistor having a control terminal coupled to a differential input terminal of the amplifier stage, a first conduction terminal coupled to a high reference voltage source and a second conduction terminal, the first conduction terminal being unconnected to the other half cell;

a second transistor having a control terminal, a first conduction terminal coupled thereto so as to form a diode-connected transistor, and a second conduction terminal coupled to the second conduction terminal of the first transistor, the output terminal appearing at the first conduction terminal of the second transistor;

a first current source providing a current to the first conduction terminal of the second transistor; and

a second current source sinking a current from the second terminal of the first and second transistors.

9. The delay line of claim 8, wherein said amplifier stage has no negative feedback.

10. A transverse time-continuous analog filter comprising:

at least one delay line, said delay line comprising;

a cascade of cells, each cell having a fully differential amplifier stage inserted between a first reference supply voltage and a second reference voltage, said amplifier stage having at least one input terminal and at least one output terminal;

wherein said amplifier stage comprises a pair of structurally identical half-cells, each provided with a transconductance amplifier stage and each connected through a respective capacitor to a common circuit node, each half cell comprising;

a first transistor having a control terminal coupled to a differential input terminal of the amplifier stage, a first conduction terminal coupled to a high reference voltage source and a second conduction terminal, the first conduction terminal being unconnected to the other half cell;

a second transistor having a control terminal, a first conduction terminal coupled thereto so as to form a diode-connected transistor, and a second conduction terminal coupled to the second conduction terminal of the first transistor, the output terminal appearing at the first conduction terminal of the second transistor;

a first current source providing a current to the first conduction terminal of the second transistor; and

a second current source sinking a current from the second terminal of the first and second transistors.

11. The filter of claim 10 comprising a cascade of identical delay lines connected through multiplier circuits to a final summation circuit.

12. The filter of claim 10, wherein said amplifier stage has no negative feedback.

13. An elementary cell structure for time-continuous analog filters an in particular for the processing of analog signals in read/write operations on magnetic supports, including a fully differential amplifier inserted between a first reference supply voltage and a second reference voltage and having at least one input terminal and at least one output terminal, said amplifier comprising an input stage coupled to said at least one input terminal and having a pair of structurally identical half stage input circuits coupled to a first common node through a respective first capacitor, and an output stage coupled to said at least one output terminal and having a pair of structurally identical half stage output circuits, said half stage output circuits being connected to a second common circuit node through a respective second capacitor, each of the half stage input circuits being connected in cascade relation to a respective half stage output circuit at an input thereof, each half stage input circuit comprising a first transistor having a control terminal coupled to said at least one input terminal, a first conduction terminal coupled to a high reference voltage source and a second conduction terminal, the first conduction terminal being unconnected to the other half stage input circuit, a second transistor having a control terminal, a first conduction terminal coupled thereto so as to form a diode-connected transistor, and a second conduction terminal coupled to the second conduction terminal of the first transistor, a first current source providing a current to the first conduction terminal of the second transistor, and a second current source sinking a current from the second terminal of the first and second transistors.

14. The cell structure of claim 13, wherein said amplifier stage has no negative feedback.

15. The elementary cell structure of claim 13, wherein each half stage output circuit comprises differential amplifier circuit.

16. A time-continuous integrated circuit filter structure, comprising:

a plurality of substantially identical fully differential analog transconductor delay cells which are mutually interconnected through respect capacitors along a signal path, each delay cell comprising;

an input stage comprising a pair of substantially structurally identical half input stages connected to a first common node through a respective first capacitor, each half input stage comprising;

a first transistor having a control terminal coupled to an input of the delay cell, a first conduction terminal coupled to a high reference voltage source and a second conduction terminal, the first conduction terminal being unconnected to the other hale input stage;

a second transistor having a control terminal, a first conduction terminal coupled thereto so as to form a diode-connected transistor, and a second conduction terminal coupled to the second conduction terminal of the first transistor, an output of the half input stage appearing at the first conduction terminal of the second transistor; and

a first current source sinking a current from the second terminal of the first and second transistors;

an output stage connected in cascade relation to the input stage and comprising a pair of substantially structurally identical half output stages connected to a second common node through a respective second capacitor; and

an analog combining stage operatively connected to receive and combine outputs of said delay cells in a circuit relation which implements a transversal filter function.

17. The integrated circuit of claim 16, wherein said analog combining stage is an analog summation stage.

18. The integrated circuit of claim 16, wherein said transconductor delay stages are connected in series to receive and pass along an external input signal.

19. The integrated circuit of claim 16, wherein said transconductor delay stages are interconnected in series with said respective multiplying stages and in parallel with each other.

20. The integrated circuit of claim 16, wherein each said transconductor delay stage contains an active device circuit configuration which is identical to that of others of said transconductor delay stages.

21. The integrated circuit of claim 16, wherein all said transconductor delay stages are identical.

22. The integrated circuit of claim 16, wherein said transconductor delay stages have identical circuit typology but include delay-determining capacitors of different respective values.

23. A time-continuous filter integrated circuit, comprising:

a plurality of transconductor delay stages which are all topologically similar to each other and which each include at least one capacitor, each delay stage comprising;

an input stage comprising a pair of substantially structurally identical half input stages connected to a first common node through a respective first capacitor, each half input stage comprising;

a first transistor having a control terminal coupled to an input of the delay cell, a first conduction terminal coupled to a high reference voltage source and a second conduction terminal, the first conduction terminal being unconnected to the other half input stage;

a second transistor having a control terminal, a first conduction terminal coupled thereto so as to form a diode-connected transistor, and a second conduction terminal coupled to the second conduction terminal of the first transistor, an output of the half input stage appearing at the first conduction terminal of the second transistor; and

a first current source sinking a current from the second terminal of the first and second transistors;

an output stage connected in cascade relation to the input stage and comprising a pair of substantially structurally identical half output stages connected to a second common node through a respective second capacitor;

a plurality of analog multiplying stages each connected to the output of a respective one of said transconductor delay stages, ones of said multiplying stages being connected to receive gain values from respective control lines; and

an analog combining stage operatively connected to receive and combine outputs of said analog multiplying stages in a relation which implements a desired transversal filter function.

24. The integrated filter circuit of claim 23, wherein said analog combining stage is an analog summation stage.

25. The integrated filter circuit of claim 23, wherein said transconductor delay stages are connected in series to receive and pass along an external input signal.

26. The integrated filter circuit of claim 23, wherein said transconductor delay stages are interconnected in a series-parallel relationship.

27. The integrated filter circuit of claim 23, wherein each said transconductor delay stage contains an active device circuit configuration which is identical to that of others of said transconductor delay stages.

28. The integrated filter circuit of claim 23, wherein all said transconductor delay stages are identical.

29. The integrated filter circuit of claim 23, wherein said transconductor delay stages have identical circuit typology but include delay-determining capacitors of different respective values.