Complementary pair-configured telecommunication line driver having synthesized output impedance

• US 6,359,505 B1
• Filed: 12/19/2000
• Issued: 03/19/2002
• Est. Priority Date: 12/19/2000
• Status: Expired due to Term

• Current Assignee: ADTRAN Incorporated (ADTRAN Holdings, Inc.)
• Original Assignee: ADTRAN Incorporated (ADTRAN Holdings, Inc.)
• Inventors: Joffe, Daniel M.
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Choe, Henry
• Application Number:
  US09/781,566
• Time in Patent Office: 455 Days
• Field of Search: 330/69, 330/103, 330/104, 330/165, 330/195
• US Class Current: 330/69
• CPC Class Codes: H03F 1/565 using inductive elements
• CPC Class Codes: H03F 2200/423 Amplifier output adaptation especially for transmission line coupling purposes, e.g. impedance adaptation
• CPC Class Codes: H03F 2200/541 Transformer coupled at the output of an amplifier
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H04L 25/0266 Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling

Abstract

A synthetic impedance line driver for driving a telecommunication line includes a complementary operational amplifier pair having cross-coupled positive feedback summing resistors. The driver circuit is configured to provide a relatively large multiplication of the values of relatively small valued output resistors to realize a synthesized impedance matching that of the driven line. A cross-coupled resistor network may be employed to cancel out far end signal components present in an analog canceler drive signal. The values of the auxiliary network resistors are ratioed such that the signal at nodes between resistors of branches of the network is a fraction of the open circuit voltage swing of the amplifiers, with far end signal components canceled.

Claims

1. A driver amplifier circuit comprising:

a first operational amplifier having first and second differential polarity inputs and an output, said first differential polarity input of said first operational amplifier being coupled to a first reference potential terminal;

a first input resistor coupling said second differential polarity input of said first operational amplifier to a first of complementary input terminals to which an input signal is applied;

a first negative feedback resistor coupled between said output and said second input of said first operational amplifier;

a first output resistor coupled between said output of said first operational amplifier and a first output terminal to which a load being driven is coupled;

a second operational amplifier having first and second differential polarity inputs and an output, said first differential polarity input of said second operational amplifier being coupled to said first reference potential terminal;

a second input resistor coupling said second differential polarity input of said second operational amplifier to a second of said complementary input terminals;

a second negative feedback resistor coupled between said output and said second input of said second operational amplifier;

a second output resistor coupled between said output of said second operational amplifier and second output terminal to which said load is coupled;

a first positive feedback resistor cross-coupled between said first output terminal and said second differential polarity input of said second operational amplifier; and

a second positive feedback resistor cross-coupled between said second output terminal and said second differential polarity input of said first operational amplifier.

2. A driver amplifier according to claim 1, wherein values of said first and second output resistors are on the order of multiple orders of magnitude smaller than values of said input and feedback resistors.

3. A driver amplifier circuit according to claim 1, further including a resistor network cross-coupled between opposite ends of said first and second output resistors.

4. A driver amplifier circuit according to claim 3, wherein said resistor network includes a first plurality of series connected resistors coupled between one end of said first output resistor and an opposite end of said second output resistor, and a second plurality of series connected resistors coupled between one end of said second output resistor and an opposite end of said first output resistor.

5. A driver amplifier circuit according to claim 4, wherein respective first and second nodes of said first and second pluralities of series connected resistors are adapted to be coupled to an analog signal cancellation circuit.

6. A driver amplifier circuit according to claim 4, wherein values of said series connected resistors are ratioed such that a signal at nodes therebetween is a prescribed fraction of the open circuit voltage swing of said operational amplifiers, with far end signal components canceled.

7. A driver amplifier circuit comprising first and second operational amplifiers having differential polarity inputs respectively coupled to a reference potential and through input resistors to complementary input terminals, respective negative feedback resistors coupled between outputs and inputs of said operational amplifiers, first and second output resistors coupled between said outputs of said operational amplifiers and first and second output terminals, and first and second positive feedback resistors cross-coupling said first and second output terminals with inputs of said operational amplifiers.

8. A driver amplifier according to claim 7, wherein values of said first and second output resistors are on the order of multiple orders of magnitude smaller than values of said input and feedback resistors.

9. A driver amplifier circuit according to claim 7, further including a resistor network cross-coupled between opposite ends of said first and second output resistors.

10. A driver amplifier circuit according to claim 9, where in s aid resistor network includes first series connected resistors coupled between one end of said first output resistor and an opposite end of said second output resistor, and second series connected resistors coupled between one end of said second output resistor and an opposite end of said first output resistor.

11. A driver amplifier circuit according to claim 9, wherein respective first and second nodes of said first and second series connected resistors are adapted to be coupled to an analog signal cancellation circuit.

12. A driver amplifier circuit according to claim 11, wherein values of said series connected resistors are ratioed such that a signal at nodes of branches of said network is a prescribed fraction of the open circuit voltage swing of said operational amplifiers, with far end signal components canceled.

13. A method of driving a telecommunication line comprising the steps of:

(a) providing a complementary line driver circuit that is configured to present to a driven line with an impedance that effectively matches that of said line, said complementary line driver including

a first operational amplifier having first and second differential polarity inputs and an output, said first differential polarity input of said first operational amplifier being coupled to a first reference potential terminal,

a first input resistor coupling said second differential polarity input of said first operational amplifier to a first of complementary input terminals,

a first negative feedback resistor coupled between said output and said second input of said first operational amplifier,

a first output resistor coupled between said output of said first operational amplifier and a first output terminal to which a load being driven is coupled,

a second operational amplifier having first and second differential polarity inputs and an output, said first differential polarity input of said second operational amplifier being coupled to said first reference potential terminal,

a second input resistor coupling said second differential polarity input of said second operational amplifier to a second of said complementary input terminals,

a second negative feedback resistor coupled between said output and said second input of said second operational amplifier,

a second output resistor coupled between said output of said second operational amplifier and second output terminal to which said load is coupled,

a first positive feedback resistor cross-coupled between said first output terminal and said second differential polarity input of said second operational amplifier, and

a second positive feedback resistor cross-coupled between said second output terminal and said second differential polarity input of said first operational amplifier;

(b) transformer-coupling said first and second output terminals to said line; and

(c) applying an input signal across said complementary input terminals.

14. A method according to claim 13, wherein values of said first and second output resistors are on the order of multiple orders of magnitude smaller than values of said input and feedback resistors.

15. A method according to claim 13, wherein said complementary line driver further includes a resistor network cross-coupled between opposite ends of said first and second output resistors.

16. A method according to claim 14, wherein said resistor network includes a first plurality of series connected resistors coupled between one end of said first output resistor and an opposite end of said second output resistor, and a second plurality of series connected resistors coupled-between one end of said second output resistor and an opposite end of said first output resistor.

17. A method according to claim 16, wherein respective first and second nodes of said first and second pluralities of series connected resistors are coupled to an analog signal cancellation circuit.

18. A method according to claim 15, wherein values of said series connected resistors are ratioed such that a signal at nodes therebetween is a prescribed fraction of the open circuit voltage swing of said operational amplifiers, with far end signal components canceled.