Circuit arrangement for index and control functions of a television apparatus

• US 6,359,655 B1
• Filed: 04/07/1997
• Issued: 03/19/2002
• Est. Priority Date: 04/17/1996
• Status: Expired due to Fees

• Current Assignee: Entropic Communications Incorporated (Maxlinear Incorporated)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Plog, Jürgen, Van Vignau, Ralph
• Primary Examiner(s): Lee, Michael
• Assistant Examiner(s): Lo, Linus H.
• Application Number:
  US08/838,489
• Time in Patent Office: 1,807 Days
• Field of Search: H04/N.700, H04/N 1.100, 348/468, 348/461, 348/478, 348/473, 348/563, 348/564, 348/569, 348/567, 348/488, 348/714, 358/147, 358/142
• US Class Current: 348/468
• CPC Class Codes: H04N 5/44504 Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 7/0884 for the transmission of additional display-information, e.g. menu for programme or channel selection

Abstract

For a possible flexible adaptation to changing ambient conditions, a circuit arrangement comprising an integrated circuit in which a microprocessor is provided which controls an index generator provided in the integrated circuit for teletext and/or on-screen display functions and which performs control functions of a television apparatus by means of a control interface provided in the integrated circuit is characterized in that a storage interface for a read-only memory outside the integrated circuit is provided in the integrated circuit, and in that the read-only memory comprises at least a part of the program code for the microprocessor and at least a font for the teletext function and possible further index functions.

Claims

1. A television display circuit arrangement comprising

an integrated circuit and a read only memory, said integrated circuit comprising:

a microprocessor for controlling functions of the integrated circuit including the display of on-screen fonts;

a single storage interface for said read-only memory; and

a storage unit for temporary storage of hi-resolution graphics and/or a graphic cursor, wherein there is a direct exchange of data between the storage unit and the storage interface for the read-only memory;

the read only memory located external to the integrated circuit for storing at least a part of the program code for the microprocessor and at least a font to be displayed on-screen, as well as data from which arbitrary pixel graphics having a preselectable pixel and color resolution can be generated in a software-controlled manner and given a format which is suitable for display.

2. A circuit arrangement as claimed in claim 1, wherein operating system software is provided for the microprocessor, which software is at least partly stored in the external read-only memory and has a software interface on which application programs can be set up, which are stored exclusively in the external read-only memory.

3. A circuit arrangement as claimed in claim 1 wherein the integrated circuit is provided with a data reception unit via which teletext data, videotext data and/or format and display data are received from a receiving unit of the television apparatus, said received data being identified and A/D converted in the data reception unit, and in that the digital data supplied by the A/D converter of the reception unit of the integrated circuit are decoded in a software-controlled manner by means of the microprocessor and further processed in accordance with their identified type.

4. A circuit arrangement as claimed in claim 1, further including an index generator wherein the index generator is implemented for building up arbitrary graphics, whose output data are applied to the integrated circuit from the read-only memory.

5. A circuit arrangement as claimed in claim 1, wherein a data decoder for special functions comprising at least one of decoding, error correction, and decrypting encrypted programs is provided in the integrated circuit.

6. A circuit arrangement as claimed in claim 1, wherein a data decoder continuously subjects data supplied thereto to the decoding process, and in that the output data of the decoder are only requested when encoded data are concerned.

7. A circuit arrangement as claimed in claim 1, wherein the integrated circuit is provided with a synchronizing unit which generates clock signals of different frequencies required in the integrated circuit from an externally supplied clock signal.

8. A circuit arrangement as claimed in claim 1, wherein a synchronizing unit varies the frequency of clock signals generated for an index generator, dependent on index parameters corresponding to a selected graphic.

9. A circuit arrangement as claimed in claim 2, wherein the integrated circuit is provided with a data reception unit via which at least one of teletext data, videotext data, and format and display data are received from a receiving unit of a television apparatus, said received data being identified and A/D converted in the data reception unit, and in that the digital data supplied by the A/D converter of the reception unit of the integrated circuit are decoded in a software-controlled manner by means of the microprocessor and further processed in accordance with their identified type.

10. A circuit arrangement as claimed in claim 2, further including an index generator wherein the index generator is implemented for building up arbitrary graphics, whose output data are applied to the integrated circuit from the read-only memory.

11. A circuit arrangement as claimed in claim 3, further including an index generator wherein the index generator is implemented for building up arbitrary graphics, whose output data are applied to the integrated circuit from the external read-only memory.

12. A circuit arrangement as claimed in claim 4, wherein arbitrary pixel graphics are generated in a software-controlled manner by means of the microprocessor from output data stored in the external read-only memory, which pixel graphics have a preselectable pixel and color resolution and, after temporary storage, are given a format which is suitable for indication by means of the index generator.

13. A circuit arrangement as claimed in claim 12, wherein a data decoder for special functions comprising at least one of decoding, error correction, and decrypting encrypted programs is provided in the integrated circuit.

14. A circuit amendment as claimed in claim 10 wherein a data decoder continuously subjects data supplied thereto to the decoding process, and in that output data of the decoder are only requested when encoded data are concerned.

15. A circuit arrangement as claimed in claim 13, wherein the integrated circuit is provided with a synchronizing unit which generates clock signals of different frequencies required in the integrated circuit from an externally supplied clock signal.

16. A circuit arrangement as claimed in claim 7, wherein the synchronizing unit varies the frequency of the clock signals generated for an index generator dependent on index parameters corresponding to a selected graphic.