Clock conversion apparatus and method

• US 6,359,910 B1
• Filed: 07/07/1997
• Issued: 03/19/2002
• Est. Priority Date: 07/04/1996
• Status: Expired due to Term

• Current Assignee: Sovereign Peak Ventures, LLC (Dominion Harbor Enterprises, LLC)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Takahashi, Toshiya
• Primary Examiner(s): Chin, Wellington
• Assistant Examiner(s): NGUYEN, STEVEN H D
• Application Number:
  US08/888,914
• Time in Patent Office: 1,716 Days
• Field of Search: 370/516, 370/503, 370/512, 370/535, 370/537, 370/538, 370/509, 370/517, 348/423, 348/429, 348/473, 348/474, 348/423.1, 348/429.1, 375/354, 375/355, 375/356, 375/359, 386/95, 386/98, 386/101, 386/109
• US Class Current: 370/535
• CPC Class Codes: H04N 19/30 using hierarchical techniques, e.g. scalability H04N19/63 takes precedence
• CPC Class Codes: H04N 21/234318 by decomposing into objects, e.g. MPEG-4 objects
• CPC Class Codes: H04N 21/2368 Multiplexing of audio and video streams
• CPC Class Codes: H04N 21/242 Synchronization processes, e.g. processing of PCR [Program Clock References] arrangements for synchronising broadcast or distribution via plural systems in broadcast distribution systems H04H20/18
• CPC Class Codes: H04N 21/4302 Content synchronisation processes, e.g. decoder synchronisation
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/43072 of multiple content streams on the same device
• CPC Class Codes: H04N 21/4341 Demultiplexing of audio and video streams
• CPC Class Codes: H04N 21/44004 involving video buffer management, e.g. video decoder buffer or video display buffer
• CPC Class Codes: H04N 7/52 Systems for transmission of a pulse code modulated video signal with one or more other pulse code modulated signals, e.g. an audio signal or a synchronizing signal assembling of a multiplex stream by combining a video stream with other content or additional data, remultiplexing of multiplex streams, insertion of stuffing bits into the multiplex stream, assembling of a packetised elementary stream at server side H04N21/236; disassembling of a multiplex stream, remultiplexing of multiplex streams, extraction or processing of Service Information, disassembling of packetised elementary stream at client side H04N21/434

Abstract

A multiplexed data producing apparatus which multiplexes N (integer) pieces of object data in which one of video data, audio data, and digital data is multiplexed to produce one piece of multiplexed data comprises a temporal storage means for temporarily storing the N pieces of object data; a control means for controlling synchronization of time information of each object data for each temporarily stored object data; and a multiplexing means for multiplexing the processed object data to produce multiplexed data.

Claims

1. A clock conversion apparatus for converting clock information included in encoded digital data in which one of video data, audio data, and text data is compressively encoded, said apparatus comprising:

storage means for storing N pieces of encoded digital data, each of said N pieces of encoded digital data including clock information from an encoding apparatus that encoded said encoded digital data, said storage means comprising a plurality of buffers for temporarily storing encoded digital data switchably connected to a memory for storing an encoded digital data for clock conversion; and

a clock conversion means comprising a clock generating circuit for generating a clock signal, a clock renewal circuit for renewing clock information of encoded digital data stored in said memory, and a CPU for controlling transmission of the encoded digital data from a buffer to the memory and renewal of the clock renewal circuit.

2. The clock conversion apparatus of claim 1 wherein employed as a clock of this clock conversion apparatus is a clock which is not synchronized with any of the clock information of the N pieces of encoded digital data.

3. The clock conversion apparatus of claim 1 wherein employed as a clock of this clock conversion apparatus is a clock which is synchronized with at least one of the clock information of the N pieces of encoded digital data.

4. The clock conversion apparatus of claim 1 wherein the N pieces of encoded digital data are multiplexed and then output.

5. An encoded data reproducing apparatus for decoding encoded digital data in which at least one of video data, audio data, and text data is compressively encoded, to reproduce one of video data, audio data, and text data,

wherein encoded digital data processed in a clock conversion apparatus as defined in claim 1 is employed as the decoding target, and the same clock is used for the decoding.

6. An encoded data recording medium in which encoded digital data obtained by compressive encoding of one of video data, audio data, and text data is recorded:

wherein encoded digital data processed in a clock conversion apparatus as defined in claim 1 is recorded.

7. An encoded data transmitting medium in which encoded digital data obtained by compressive encoding of one of video data, audio data, and text data is transmitted:

wherein encoded digital data processed in a clock conversion apparatus as defined in claim 1 is transmitted.

8. A clock conversion method for converting clock information included in encoded digital data in which one of video data, audio data, and text data is compressively encoded, said method comprising:

inputting N pieces of encoded digital data into a first buffer of a storage unit;

reading the N pieces of encoded digital data from said first buffer into a memory according to a transmission clock for compressive encoding;

reading the N pieces of encoded digital data from the memory into a clock renewal circuit;

renewing clock information included in said N pieces of encoded digital data using a clock generated by a clock generating circuit to create a renewed encoded digital data; and

outputting said renewed first encoded digital data from said clock renewal circuit;

wherein multiplexed data on the basis of the renewed N pieces of encoded digital data is output from said clock conversion apparatus.

9. The clock conversion method of claim 8 wherein employed as a clock of this clock conversion method is a clock which is not synchronized with any of the clock information of the N pieces of encoded digital data.

10. The clock conversion method of claim 8 wherein employed as a clock of this clock conversion method is a clock which is synchronized with at least one of the clock information of the N pieces of encoded digital data.

11. The clock conversion method of claim 8 wherein the N pieces of encoded digital data are multiplexed and then output.

12. An encoded data reproducing method for decoding encoded digital data in which at least one of video data, audio data, and text data is compressively encoded, to reproduce one of video data, audio data, and text data,

wherein encoded digital data processed in a clock conversion method as defined in claim 8 is employed as the decoding target, and the same clock is used for the decoding.

13. A clock conversion method for converting clock information included in encoded digital data in which one of video data, audio data, and text data is compressively encoded, said method comprising:

inputting a first encoded digital data into a first buffer of a storage unit;

reading the first encoded digital data from said first buffer into a memory according to a first transmission clock;

inputting a second encoded digital data into a second buffer of the storage unit;

reading the second encoded digital data from said second buffer into said memory according to a second transmission clock;

reading the first encoded digital data from the memory into a clock renewal circuit;

renewing clock information included in said first encoded digital data using a clock generated by a clock generating circuit to create a renewed first encoded digital data;

outputting said renewed first encoded digital data from said clock renewal circuit;

reading the second encoded digital data from the memory into said clock renewal circuit;

renewing clock information included in said second encoded digital data using said clock generated by the clock generating circuit to create a renewed second encoded digital data; and

outputting said renewed second encoded digital data from said clock renewal circuit.

14. A clock conversion method for converting clock information included in encoded digital data in which one of video data, audio data, and text data is compressively encoded, said method comprising:

storing N pieces of encoded digital data in storage means, each including clock information of an encoding apparatus used for the compressive encoding;

reading each of the N pieces of encoded digital data from the storage means using a clock generated by a clock generating circuit;

renewing clock information included in each of the N pieces of encoded digital data read from the storage means using the clock to create N pieces of renewed encoded digital data; and

outputting the renewed N pieces of encoded digital data including the same clock information.