Single chip VLSI implementation of a digital receiver employing orthogonal frequency division multiplexing

• US 6,359,938 B1
• Filed: 10/22/1997
• Issued: 03/19/2002
• Est. Priority Date: 10/31/1996
• Status: Expired due to Term

• Current Assignee: Chartoleaux KG LLC (Intellectual Ventures LLC)
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Collins, Matthew, Foxcroft, Thomas, Davies, David H., Parker, Jonathan, Alam, Dawood, Keevill, Peter A, Nolan, John M.
• Primary Examiner(s): Pham, Chi H.
• Assistant Examiner(s): Bayard, Emmanuel
• Application Number:
  US08/956,300
• Time in Patent Office: 1,609 Days
• Field of Search: 375/316, 375/260, 375/259, 375/340, 375/329, 375/331, 375/332, 370/206, 370/208, 370/210, 370/491, 370/480, 370/500, 370/478, 370/343, 370/344, 364/726.01, 364/726.02, 364/726.03
• US Class Current: 375/316
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0065 Serial concatenated codes
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 25/0214 of a single coefficient
• CPC Class Codes: H04L 25/0232 by interpolation between sounding signals
• CPC Class Codes: H04L 27/26524 Fast Fourier transform [FFT] or discrete Fourier transform [DFT] demodulators in combination with other circuits for demodulation
• CPC Class Codes: H04L 27/2657 Carrier synchronisation
• CPC Class Codes: H04L 27/2662 Symbol synchronisation

Abstract

The invention provides a single chip implementation of a digital receiver for multicarrier signals that are transmitted by orthogonal frequency division multiplexing. Improved channel estimation and correction circuitry are provided. The receiver has highly accurate sampling rate control and frequency control circuitry. BCH decoding of tps data carriers is achieved with minimal resources with an arrangement that includes a small Galois field multiplier. An improved FFT window synchronization circuit is coupled to the resampling circuit for locating the boundary of the guard interval transmitted with the active frame of the signal. A real-time pipelined FFT processor is operationally associated with the FFT window synchronization circuit and operates with reduced memory requirements.

Claims

1. A digital receiver for multicarrier signals, said receiver comprising:

an amplifier accepting an analog multicarrier signal, said multicarrier signal including a stream of data symbols having a symbol period T_S, the symbols having an active interval, a guard interval, and a boundary therebetween, said guard interval being a replication of a portion of said active interval;

an analog to digital converter coupled to said amplifier;

an I/Q demodulator for recovering in phase and quadrature components from data sampled by said analog to digital converter;

an automatic gain control circuit coupled to said analog to digital converter for providing a gain control signal for said amplifier;

a low pass filter circuit accepting I and Q data from said I/Q demodulator, said I and Q data being decimated therein;

a resampling circuit receiving said decimated I and Q data at a first rate and outputting resampled I and Q data at a second rate;

an FFT window synchronization circuit coupled to said resampling circuit for locating a boundary of said guard interval;

a real-time pipelined FFT processor operationally associated with said FFT window synchronization circuit, said FFT processor including at least one stage; and

a monitor circuit responsive to said FFT window synchronization circuit for detecting a predetermined event, said event thereby indicating that a boundary between an active symbol and a guard interval has been located.

2. The receiver according to claim 1 wherein said FFT window synchronization circuit comprises:

a first delay element accepting currently arriving resampled I and Q data, and outputting delayed resampled I and Q data;

a subtracter for producing a difference signal representative of a difference between said currently arriving resampled I and Q data and said delayed resampled I and Q data;

a first circuit for producing an output signal having a unipolar magnitude that is representative of said difference signal of said subtracter;

a second delay element for storing said output signal of said first circuit;

a third delay element receiving delayed output of said second delay element; and

a second circuit for calculating a statistical relationship between data stored in said second delay element and data stored in said third delay element and having an output representative of said statistical relationship.

3. The receiver according to claim 2 wherein said statistical relationship includes an F ratio.

4. The receiver according to claim 1 wherein said FFT processor operates in an 8K mode.

5. The receiver according to claim 1 wherein said FFT processor includes an address generator for said memory, said address generator accepting a signal representing an order dependency of a currently required multiplicand, and outputting an address of said memory so that said currently required multiplicand is stored.

6. The receiver according to claim 5 wherein each of said multiplicands is stored in said lookup table based on its respective order dependency for multiplication by said complex coefficient multiplier, said order dependencies of said multiplicands defining an incrementation sequence, and said address generator comprises:

an accumulator for storing a previous address that was generated by said address generator;

a circuit for calculating an incrementation value of said currently required multiplicand; and

an adder for adding said incrementation value to said previous address.

7. The receiver according to claim 6 wherein said lookup table includes a plurality of rows, said incrementation sequence includes a plurality of incrementation sequences, and said multiplicands are stored in row order in accord with the following:

in a first row a first incrementation sequence is 0;

in a second row a second incrementation sequence is 1;

in a third row first and second break points B1 and B2 of a third incrementation sequence are respectively determined by the relationships, $B_{1_{M_N}}=4^N<br><br>{\mathrm{B1}}_{M_N}-\underset{n=0}{\overset{N-1}{\sum <br><br>}}<br><br>4^n<br><br>\text{\hspace{1em}<br><br>}<br><br>B_{2_{M_N}}=\underset{n=0}{\overset{N}{\sum <br><br>}}<br><br>4^n;<br><br>\mathrm{and}$

in a fourth row a third break point B3 of a third incrementation sequence is II determined by the relationship,

8. The receiver according to claim 1 further comprising channel estimation and correction circuitry including pilot location circuitry receiving a transformed digital signal representing a frame from said FFT processor for locating pilot carriers therein, said pilot carriers being spaced apart in a carrier spectrum of said transformed digital signal at intervals K and having predetermined magnitudes.

9. The receiver according to claim 8 wherein said pilot location circuitry further includes a bit reversal circuit for reversing bit order of said transformed digital signal.

10. The receiver according to claim 8 wherein at least one of said predetermined magnitudes of said carriers defines an amplitude.

11. The receiver according to claim 8 wherein said magnitudes of said carriers and said predetermined magnitudes are absolute values.

12. The receiver according to claim 8 wherein said channel estimation and correction circuitry includes:

an interpolating filter for estimating a channel response between said pilot carriers; and

a multiplication circuit for multiplying data carriers output by said FFT processor with a correction coefficient produced by said interpolating filter.

13. The receiver according to claim 8 wherein said channel estimation and correction circuitry includes a phase extraction circuit accepting a data stream of phase-uncorrected I and Q data from said FFT processor to thereby produce a signal representative of a phase angle of said uncorrected data, said phase extraction circuit including an accumulator for accumulating the phase angles of succeeding phase-uncorrected I and Q data.

14. The receiver according to claim 13 wherein said channel estimation and correction circuitry includes an automatic frequency control circuit coupled to said phase extraction circuit and said accumulator.

15. The receiver according to claim 13 wherein said channel estimation and correction circuitry further includes an automatic sampling rate control circuit coupled to said phase extraction circuit.

16. The receiver according to claim 15 wherein said sampling rate control circuit stores a plurality of accumulated intersymbol carrier phase error differentials and computes a line of best fit therebetween.

17. The receiver according to claim 15 wherein a common memory for storing output of said phase extraction circuit is coupled to said automatic sampling rate control circuit.

18. The receiver according to claim 13 wherein said phase extraction circuit includes a pipelined circuit for iteratively computing the arctangent of an angle of rotation according to the series ${\tan }^{-1}$

(x)=x-x33+x55-x77+x99-…



 

,

x

<

1

where x is a ratio of said phase-uncorrected I and Q data.

19. The receiver according to claim 18 wherein said pipelined circuit includes:

a constant coefficient multiplier;

and a multiplexer for selecting one of a plurality of constant coefficients of said series, an output of said multiplexer being connected to an input of said constant coefficient multiplier.

20. The receiver according to claim 18 wherein said pipelined circuit includes:

a multiplier;

a first memory for storing the quantity x², said first memory being coupled to a first input of said multiplier;

a second memory for holding an output of said multiplier; and

a feedback connection between said second memory and a second input of said multiplier.

21. The receiver according to claim 18 wherein said pipelined circuit further includes:

a third memory for storing a value of said series;

a control circuit coupled to said third memory, said pipeline circuit computing N terms of said series, and N+1 terms of said series, where N is an integer;

an averaging circuit coupled to said third memory for computing an average of said N terms and said N+1 terms of said series.

22. The receiver according to claim 1 wherein data transmitted in a pilot carrier of said multicarrier signal is BCH encoded according to a code generator polynomial h(x).

23. The receiver according to claim 1 wherein said at least one stage of said FFT processor includes a complex coefficient multiplier, and a memory having a lookup table defined therein for multiplicands being multiplied in said complex coefficient multiplier, a value of each said multiplicand being unique in said lookup table.

24. The receiver according to claim 15 wherein said automatic frequency control circuit includes a memory for storing an accumulated common phase error of a first symbol carried in said phase-uncorrected I and Q data.

25. The receiver according to claim 24 wherein said accumulator is coupled to said memory and accumulates a difference between a common phase error of a plurality of pilot carriers in a second symbol and a common phase error of corresponding pilot carriers in said first symbol.

26. The receiver according to claim 25 wherein an output of said accumulator is coupled to said I/Q demodulator.

27. The receiver according to claim 26 wherein said coupled output of said accumulator is enabled in said I/Q demodulator only during reception of a guard interval therein.

28. The receiver according to claim 15 wherein said automatic sampling rate control circuit includes a memory for storing accumulated phase errors of pilot carriers in a first symbol carried in said phase-uncorrected I and Q data.

29. The receiver according to claim 28 wherein a coupled output signal of said accumulator is enabled in said resampling circuit only during reception of a guard interval therein.

30. The receiver according to claim 28 wherein said accumulator is coupled to said memory and accumulates differences between phase errors of pilot carriers in a second symbol and phase errors of corresponding pilot carriers in said first symbol to define a plurality of accumulated intersymbol carrier phase error differentials.

31. The receiver according to claim 30 wherein a phase slope is defined by a difference between a first accumulated intersymbol carrier phase differential and a second accumulated intersymbol carrier phase differential.

32. The receiver according to claim 6 wherein an output of said accumulator is coupled to said I/Q demodulator.

33. The receiver according to claim 17 further including an automatic frequency control circuit coupled to said phase extraction circuit and said automatic sampling rate control circuit.

34. The receiver according to claim 22 further including a demodulator operative on said BCH encoded data.

35. The receiver according to either claim 22 or 34 further including an iterative pipelined BCH decoding circuit.

36. The receiver according to claim 35 wherein said iterative pipelined BCH decoding circuit includes a circuit coupled to said demodulator for forming a Galois Field of said polynomial, and calculating a plurality of syndromes therewith.

37. The receiver according to claim 36 wherein said iterative pipelined BCH decoding circuit further includes a plurality of storage registers, each said storage register storing a respective one of said syndromes.

38. The receiver according to claim 37 wherein said iterative pipelined BCH decoding circuit further includes a plurality of feedback shift registers, each said feedback shift register accepting data from a respective one of said storage registers and having an output.

39. The receiver according to claim 38 wherein said iterative pipelined BCH decoding circuit further includes a plurality of Galois field multipliers, each of said multipliers being connected in a feedback loop across a respective one of said feedback shift registers and multiplying the output of its associated feedback shift register by an alpha value of said Galois Field.

40. The receiver according to claim 39 wherein said iterative pipelined BCH decoding circuit further includes an output Galois field multiplier for multiplying said outputs of two of said feedback shift registers.

41. The receiver according to claim 40 wherein said iterative pipelined BCH decoding circuit further includes an error detection circuit connected to said feedback shift registers and said output Galois field multiplier, an output signal of said error detection circuit enabled to indicate an error in a current bit of data.

42. The receiver according to claim 37 wherein said iterative pipelined BCH decoding circuit further includes a feedback line enabled by said error detection circuit and connected to said storage registers, outputs of said feedback shift registers thereby being written into said storage registers.

43. The receiver according to claim 40 wherein said output Galois field multiplier includes a first register initially storing a first multiplicand A.

44. The receiver according to claim 43 wherein said output Galois field multiplier further includes a constant coefficient multiplier connected to said register for multiplication by a value α

, an output of said constant coefficient multiplier being connected to said first register to define a first feedback loop so that in a kth cycle of clocked operation, said first register contains a Galois field product Aα

^k.

45. The receiver according to claim 44 wherein said output Galois field multiplier further includes a second register for storing a second multiplicand B.

46. The receiver according to claim 45 wherein said output Galois field multiplier further includes an AND gate connected to said second register and to said output of said constant coefficient multiplier.

47. The receiver according to claim 46 wherein said output Galois field multiplier further includes an adder having a first input connected to an output of said AND gate.

48. The receiver according to claim 47 wherein said output Galois field multiplier further includes an accumulator connected to a second input of said adder, an output of said adder being connected to said accumulator to define a second feedback loop so that a Galois field product AB is output by said adder.

49. The receiver according to claim 8 wherein said pilot location circuitry includes a first circuit for computing an order of carriers in said transformed digital signal modulo K.

50. The receiver according to claim 49 wherein said pilot location circuitry further includes K accumulators coupled to said first circuit for accumulating magnitudes of said carriers in said transformed digital signal, said accumulated magnitudes defining a set.

51. The receiver according to claim 50 wherein said pilot location circuitry further includes a correlation circuit for correlating K sets of accumulated magnitude values with said predetermined magnitudes, a first member having a position calculated modulo K in each of said K sets, thereby being uniquely offset from a start position of said frame.

52. The receiver according to claim 51 wherein said correlation circuit includes a peak tracking circuit for determining a spacing between a first peak and a second peak of said K sets of accumulated magnitudes.