Digital PLL (phase-locked loop) frequency synthesizer

• US 6,359,950 B2
• Filed: 03/05/2001
• Issued: 03/19/2002
• Est. Priority Date: 09/03/1998
• Status: Expired due to Fees

• Current Assignee: Siemens AG
• Original Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Inventors: Gossmann, Timo, Götz, Edmund
• Primary Examiner(s): Ghebretinsae, Temesghen
• Application Number:
  US09/799,669
• Publication Number:
  US 20010036240A1
• Time in Patent Office: 379 Days
• Field of Search: 375/376, 375/374, 327/156, 327/158, 327/147, 327/149, 331/DIG.2
• US Class Current: 375/376
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: Y10S 331/02 Phase locked loop having lock indicating or detecting means

Abstract

The circuit compensates for phase error in the case of fractional-N-based PLL frequency synthesizers. All required actuating and reference signals are derived from the VCO frequency of the voltage-controlled oscillator by using an auxiliary phase-locked loop. The circuit is specifically applicable for HF-PLL frequency synthesizers using integrated circuit technology.

Claims

1. A digital PLL frequency synthesizer, comprising:

an input receiving a signal having a stable quartz oscillator frequency;

a voltage-controlled oscillator outputting a VCO frequency;

a first PLL loop connected to an output of said voltage-controlled oscillator and an N/(N+1) frequency divider connected in said first PLL loop for dividing the VCO frequency and generating a divided VCO frequency;

a phase-frequency detector having a first input receiving the stable quartz oscillator frequency and a second input receiving the divided VCO frequency, and configured to compare the quartz oscillator frequency with the divided VCO frequency, and outputting an output signal connected as a control voltage for said voltage-controlled oscillator;

said N/(N+1) frequency divider being configured to be switched over between two adjacent integral divisor factors N and N+1, to divide by N for a duration of M-K cycles, and to divide by N+1 for a duration of K cycles;

a phase accumulator connected to said N/(N+1) frequency divider for automatically switching said N/(N+1) frequency divider, wherein a content of said phase accumulator has added thereto the value K with a modulo-M addition with each pulse of the divided VCO frequency and said phase accumulator causing a change in the divisor factor from N to N+1 in a next cycle after each overflow;

a PLL phase delay device connected between said N/(N+1) frequency divider and said second input of said phase frequency detector and to said phase accumulator, said phase delay device containing M−

1 time-delay elements in a phase delay chain and having first and second control inputs, said first control input for setting a respectively corresponding magnitude of a fundamental delay of each said time-delay element of said phase delay chain, and said second control input for setting a number of the fundamental delays to be active in said phase delay chain, wherein the contents of said phase accumulator are increased with each output pulse of said phase delay device by the adjustable fraction K of the reference frequency modulo-M, and wherein, in event of an overflow, said N/(N+1) frequency divider is switched to N+1 for a next period;

said phase accumulator having an output connected to said second control input of said phase delay device;

a further phase frequency detector having a first input, a second input connected to said output of said voltage-controlled oscillator without an interposition of a time-delay element, and an output;

a further phase delay device for simulating corresponding time-delay conditions, configured identically to said PLL phase delay device, but having a number M series-connected time-delay elements, and connected between said output of said voltage-controlled oscillator and said first input of said further phase-frequency detector; and

a further loop low pass filter connected between said output of said further phase frequency detector and said first control input of said PLL phase delay device and a control input of said further phase delay device for forming an auxiliary PLL and for setting a respectively corresponding magnitude of the fundamental delays of said time-delay elements of said PLL phase delay device and said further phase delay device.

2. The digital PLL frequency synthesizer according to claim 1, which further comprises a charge pump and a loop low-pass filter connected in said first PLL loop.

3. The frequency synthesizer according to claim 1, wherein said second control input for setting the number of the fundamental delays active in the phase delay device is formed by a control input of an M:

1 multiplexer, whereby said multiplexer selects, in dependence on a control signal present at a control input thereof, the output signal of which of the series-connected time-delay elements is decoupled and fed to said second input of said first phase-frequency detector and to said phase accumulator.

4. The frequency synthesizer according to claim 1, wherein said further phase delay device comprises dummy decoupling elements in addition to and associated with said time-delay elements for simulating the time-delay conditions corresponding to the time-delay conditions of said PLL phase delay device.

5. The frequency synthesizer according to claim 3, wherein said further phase delay device comprises dummy decoupling elements in addition to and associated with said time-delay elements for simulating the time-delay conditions corresponding to the time-delay conditions of said PLL phase delay device.

6. The frequency synthesizer according to claim 5, wherein said dummy decoupling elements are load elements simulating a loading by the input of said M:

l multiplexer of said PLL phase delay device.

7. The frequency synthesizer according to claim 1, wherein said auxiliary PLL including said further phase-frequency detector is configured with a very high loop bandwidth.

8. The frequency synthesizer according to claim 7, wherein said auxiliary PLL has a bandwidth in an order of magnitude of a bandwidth of the frequency.

9. An integrated digital PLL frequency synthesizer, which comprises the integrated frequency synthesizer according to claim 1 embodied in integrated circuit technology.