Device for generating an AC amplitude-dependent indicator

• US 6,360,086 B2
• Filed: 02/24/1999
• Issued: 03/19/2002
• Est. Priority Date: 02/26/1998
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Wagemans, Antonius G.
• Primary Examiner(s): Kincaid, Lester G.
• Assistant Examiner(s): APPIAH, CHARLES NANA
• Application Number:
  US09/257,083
• Publication Number:
  US 20010055955A1
• Time in Patent Office: 1,119 Days
• Field of Search: 455/326, 455/333, 455/69.7, 455/232.1, 455/234.1, 455/205, 455/226.4, 455/226.2, 327/58, 327/355, 327/357, 330/307, 330/195, 330/271, 324/119, 324/123.R
• US Class Current: 455/226.4
• CPC Class Codes: H03G 3/3036 in high-frequency amplifiers or in frequency-changers H03G3/3052, H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03G 3/3052 in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence

Abstract

A device for generating an indicator signal that corresponds to an AC signal amplitude is configured such that the DC current drawn by the device is substantially proportional to the AC signal amplitude. The device is particularly well suited for automatic gain control of low-power communications equipment.

Claims

1. A circuit adapted to receive an AC signal, and further adapted to provide an amplified AC signal as a first output, and to provide a signal representative of the magnitude of the received AC signal as a second output, comprising:

an AC signal input terminal coupled to a first terminal of a first capacitor;

a bias network, having one terminal coupled to a first power supply node, the bias network operable to provide current so as to produce a variable voltage at a second terminal of the bias network;

a first current-controlled semiconductor device having a first terminal, a second terminal, and a third terminal, the first terminal coupled to the second terminal of the bias network and further coupled to a second terminal of the first capacitor;

a first load element coupled in series between a second power supply node and the second terminal of the first current-controlled semiconductor device; and

a low-pass filter, coupled between the second terminal of the current-controlled semiconductor device and the second power supply node;

wherein the bias network is configured such that, in operation, the current flow in the current-controlled semiconductor device is reduced when the received AC signal is nominally zero, as compared to when the received AC signal is non-zero.

2. The circuit of claim 1, wherein the third terminal of the first current-controlled semiconductor device is couple to the first power supply node, the first current-controlled semiconductor device is a bipolar transistor, the first load element is a resistor, the low-pass filter comprises a resistor and a capacitor connected in series, and further comprising a feedback pathway between an output node of the low-pass filter and a control input terminal of the bias network.

3. The circuit of claim 2, wherein the bipolar transistor is an NPN bipolar transistor.

4. The circuit of claim 2, wherein the first power supply node is a ground node, and the second power supply node, when in operation, has a voltage thereon which is positive with respect to ground.

5. A circuit adapted to receive an AC signal, and further adapted to provide a signal representative of the magnitude of the received AC signal as a first output, comprising:

an AC signal input terminal coupled to a first terminal of a first capacitor;

a bias network, having one terminal coupled to a first power supply node, the bias network operable to provide current so as to produce a variable voltage at a second terminal of the bias network;

a first transistor having a base, a collector, and an emitter, the base coupled to the second terminal of the bias network and further coupled to a second terminal of the first capacitor;

a first load element coupled in series between a second power supply node and the collector of the first transistor;

a second transistor having a base, a collector, and an emitter, the collector of the second transistor coupled to the emitter of the first transistor, and the emitter of the second transistor coupled to the first power supply node

a third transistor having a base, a collector, and an emitter, the third transistor base couple to the second transistor base, and the third transistor emitter coupled to the first power supply node;

a second load element coupled in series between the second power supply node and the collector of the third transistor;

a fourth transistor having a base, a collector and an emitter, the fourth transistor base coupled to the first transistor collector, and the fourth transistor collector coupled to the second power supply node; and

at least one diode coupled between the fourth transistor emitter and the base of both the second and third transistors;

wherein the bias network is configured such that, in operation, the current flow in the first, second, and third transistors, is reduced when the received AC signal is zero, as compared to when the received AC signal is non-zero.

6. The circuit of claim 5, further comprising a capacitor coupled between the second power supply node and the collector of the third transistor.

7. The circuit of claim 5, wherein the at least one diode comprises two diodes coupled such that current may flow from the emitter of the fourth transistor to the bases of the second and third transistors;

and further comprising a feedback pathway coupled between a control input terminal of the bias network and the collector of the third transistor.

8. The circuit of claim 7, wherein the first, second, third, and fourth transistors are NPN transistors.

9. The circuit of claim 5, further comprising a fifth transistor having a base, a collector, and an emitter, the fifth transistor collector coupled to the second power supply node, and the fifth transistor emitter coupled to the emitter of the fourth transistor.

10. The circuit of claim 9, further comprising a sixth transistor having a base, a collector, and an emitter, the sixth transistor collector coupled to the fifth transistor base, the sixth transistor emitter coupled to the first transistor emitter, and the sixth transistor base coupled to the bias network.