Method and apparatus for producing signal processing circuits in the delta sigma domain

• US 6,360,283 B1
• Filed: 03/29/1999
• Issued: 03/19/2002
• Est. Priority Date: 06/07/1996
• Status: Expired due to Term

• Current Assignee: Powerprecise Solutions
• Original Assignee: Duality Semiconductor, Inc.
• Inventors: Houldsworth, John
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): DO, THUAN V
• Application Number:
  US09/280,053
• Time in Patent Office: 1,086 Days
• Field of Search: 341/143, 716/3, 716/4, 716/17, 716/18
• US Class Current: 710/3
• CPC Class Codes: G06F 17/10 Complex mathematical operations function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

The present invention is directed to providing a generalized system and method for enabling circuit design and fabrication in the delta sigma domain. In accordance with exemplary embodiments, a framework for such a system is based on a library of generalized operators that can receive multiple inputs, and that can be randomly chained together. Further, the operators are specifically configured to guarantee valid (e.g., bounded and/or stable) results, and to provide closure within the delta sigma domain; that is, to produce valid intermediate results in the delta sigma domain. Linear operators are configured to provide closure by complying with at least two criteria: (1) with respect to linear operators, at least one of (a) the inputs and (b) the output of a portion of the operator used to implement a mathematical function is scaled (e.g., normalized) to guarantee valid results; and (2) outputs from each mathematical operation are remodulated into a single bit stream in the delta sigma domain. Further, nonlinear operators such as multiplication operators, are configured with an eye toward producing valid results in the delta sigma domain. For example, with respect to nonlinear operators such as multipliers, at least one operand is restricted to being a non-delta sigma input (i.e., quantization noise-free). As with linear operators, the outputs from portions of nonlinear operators used to implement mathematical operations are remodulated to a single bit stream in the delta sigma domain.

Claims

1. A computer-implemented memory for use in designing a circuit, comprising:

a library of functional operators for implementing digital signal processing in the delta sigma domain, said library having at least a first functional operator and a second functional operator;

said first functional operator for implementing a first mathematical operation in the delta sigma domain;

said second function al operator for implementing a second mathematical operation in the delta sigma domain;

each mathematical operation having an input and an output; and

wherein each functional operator can be accessed by a circuit designer to implement a mathematical operation such that the processing is performed in the delta sigma domain.

2. The computer-implemented memory of claim 1, further comprising:

means for scaling one or more of the input and output of said first mathematical and said second mathematical operation to ensure a bounded result; and

means for remodulating the output of said first and second mathematical operations into the delta sigma domain.

3. The computer-implemented memory of claim 2, wherein said means for scaling is provided as part of said first functional operator and said second functional operator.

4. The computer-implemented memory of claim 2, where in said means for scaling comprises one or more separate scaling operators in said library, said one or more separate scaling operators providing scaling associated with said first functional operator and said second functional operator.

5. The computer-implemented memory of claim 2, wherein said means for remodulating comprises one or more separate remodulator operators in said library, said one or more separate remodulator operators providing remodulation associated with said first functional operator and said second functional operator.

6. The computer-implemented memory of claim 2, wherein said means for remodulating is provided as part of said first functional operator and said second functional operator.

7. The computer-implemented memory of claim 2, wherein said means for remodulating results in a multibit bitstream in the delta sigma domain, each digital word comprising multiple bits.

8. The computer-implemented memory of claim 2, wherein said means for remodulating results in a one bit bitstream in the delta sigma domain, each digital word comprising a single bit.

9. The computer-implemented memory of claim 2, wherein said scaling provides that the range of the output does not exceed the range of the input, and wherein said remodulating provides that number of bits for the output does not exceed the number of bits for the input.

10. The computer-implemented memory of claim 2, further comprising a software tool for allowing the circuit designer to represent a circuit design as a series of functional operators from said library.

11. The computer-implemented memory of claim 10, wherein said software tool comprises a commercially available capture tool.

12. The computer-implemented memory of claim 2, further comprising means for correlating a series of functional operators to an equivalent logic level description to implement a circuit design on a digital logic device.

13. The computer-implemented memory of claim 12, wherein said logic level description is VHDL.

14. The computer-implemented memory of claim 12, wherein said means for correlating comprises an analog logic translator.

15. The computer-implemented memory of claim 12, wherein said series of functional operators comprise a netlist generated by a capture tool.

16. The computer-implemented memory of claim 2, further comprising at least one supplemental operator comprising a plurality of individual functional operators linked together, and wherein the input and output of said supplemental operator is in the delta sigma domain.

17. The computer-implemented memory of claim 2, wherein said first mathematical operation is one of an addition, subtraction, multiplication, differentiation, filtering, integration, automatic gain control and decimation.

18. A method of implementing signal processing in the delta sigma domain using delta sigma operators, comprising the steps of:

providing a library of functional operators for implementing digital signal processing in the delta sigma domain, said library having at least a first functional operator and a second functional operator;

said first functional operator for implementing a first mathematical operation in the delta sigma domain;

said second functional operator for implementing a second mathematical operation in the delta sigma domain;

each mathematical operation having an input and an output; and

retrieving one or more of the functional operators in order to implement signal processing in the delta sigma domain.

19. The method of claim 18, wherein said library includes means for scaling one or more of the input and output of each mathematical operation to ensure a bounded result and means for remodulating the output of each mathematical operation into the delta sigma domain.

20. The method of claim 19, wherein said means for scaling is provided as part of said first functional operator and said second functional operator.

21. The method of claim 19, wherein said means for scaling comprises one or more separate scaling operators to be accessed to provide scaling associated with said first functional operator and said second functional operator.

22. The method of claim 19, wherein said means for remodulating is provided as part of said first functional operator and said second functional operator.

23. The method of claim 19, wherein said means for remodulating comprises one or more separate remodulator operators, said one or more separate remodulator operators providing remodulation associated with said first functional operator and said second functional operator.

24. The method of claim 19, wherein said means for remodulating results in a multibit bitstream in the delta sigma domain, each digital word comprising multiple bits.

25. The method of claim 19, wherein said means for remodulating results in a one bit bitstream in the delta sigma domain, each digital word comprising a single bit.

26. The method of claim 19, wherein said step of retrieving includes the use of a software tool for allowing a circuit designer to represent a circuit design as a series of functional operators from said library.

27. The method of claim 26, wherein said software tool comprises a commercially available capture tool.

28. The method of claim 26, wherein said software tool includes means for correlating said series of functional operators to an equivalent logic level description for implementing the circuit design on a digital logic device.

29. The method of claim 28, wherein said logic level description is VHDL.

30. The method of claim 28, wherein said means for correlating comprises an analog logic translator.

31. The method of claim 26, wherein said series of functional operators comprise a netlist generated by a capture tool.

32. The method of claim 26, wherein said software tool further comprises means to produce a routed circuit layout-based on said series of functional operators.

33. A method of employing a library of functional operators to model the performance of a circuit design implemented in the delta sigma domain, comprising the steps of:

using a software tool to represent a circuit design for implementation in the delta sigma domain as a series of functional operators from said library; and

selectively enabling and disabling a quantization noise model to evaluate the effect of implementing the circuit design in the delta sigma domain.

34. The method of claim 33, wherein said noise is added to a signal band substantially equivalent to the design signal band.

35. The method of claim 33, wherein said noise is added to a signal band of a bandwidth substantially greater than the design signal band.

36. The method of claim 33, further comprising the step of observing a time domain representation of a signal in the circuit design.

37. The method of claim 33, wherein said quantization noise model comprises the same structure to be used in a final implementation of the circuit design in the delta sigma domain.

38. The method of claim 33, wherein disabling said quantization noise model permits observation of analog implementation performance and enabling said quantization noise model permits observation of delta sigma digital implementation performance.