Commercial standard digital bus interface circuit

• US 6,360,290 B1
• Filed: 06/23/1999
• Issued: 03/19/2002
• Est. Priority Date: 06/23/1999
• Status: Expired due to Fees

• Current Assignee: United Technologies Corporation (Raytheon Technologies Corporation d/b/a RTX)
• Original Assignee: United Technologies Corporation (Raytheon Technologies Corporation d/b/a RTX)
• Inventors: Avritch, Steven A., Paul, Christopher E., Foss, Mark A.
• Primary Examiner(s): Dharia, Rupal
• Application Number:
  US09/338,722
• Time in Patent Office: 1,000 Days
• Field of Search: 710/53, 710/306, 710/305, 710/110, 710/113, 710/105, 709/249, 701/14, 701/35, 712/40, 712/37, 714/47
• US Class Current: 710/105
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Abstract

Interface apparatus is adapted for interconnection between a host computer and a Commercial Standard Digital Bus (CSDB) for translating the CSDB signal protocol of the data frames provided over the bus by different signal sources into a signal format which is compatible with the host computer.

Claims

1. Apparatus, for translating the signal protocol of serial bit message blocks presented from identified signal sources over a Commercial Standard Digital Bus (CSDB) to a host computer in each of a plurality of succeeding frames, each frame including a synchronization message block followed by one or more data message blocks, each data message block having an address byte which identifies its subject content, and a known number of data bytes, each data byte having a plurality of data bits and a parity bit, the apparatus comprising:

CSDB interface circuitry, including a serial receiver for receiving the CSDB frames and for providing each at a signal output thereof, and including detection circuitry for providing a synch enable signal in response to the presence of a synchronization message in each received frame;

control logic circuitry, including a receiver channel responsive to said signal output of said interface circuitry, for accepting and rejecting each received frame in the presence and absence, respectively, of said synch enable signal, and including decode circuitry for identifying the signal characteristics of each accepted frame message from its address byte, said receiver channel translating the CSDB signal protocol of each identified subject data byte to the signal protocol of the host computer and writing said translated protocol data byte to an assigned address location in signal memory; and

signal memory, having a plurality of addressable signal storage locations partitioned into different address groups, each said different address group storing therein translated protocol data bytes having a different signal characteristics, as written thereto by said control logic circuitry, each said group being accessible by the host computer for retrieval of said translated protocol data bytes stored therein.

2. The apparatus of claim 1:

wherein said signal characteristics identified by said decode circuitry include identification of a frame as being associated with an identified signal source, as indicated by a frame identification signal provided by said decode circuitry; and

wherein each said different address group receives and stores therein said translated protocol data bytes from an identified common signal source, as indicated by said frame identification signal.

3. The apparatus of claim 2:

wherein said signal characteristics identified by said decode circuitry further includes identification of the subject content of each message block within each identified frame, as indicated by a message identification signal provided by said decode circuitry; and

wherein each said different address group is partitioned into different address sub-groups, each said different address sub-group receiving and storing therein said translated protocol data bytes having a common subject content from a common signal source, as indicated by said frame identification signal and said message subject identification signal from said decode circuitry.

4. The apparatus of claim 3:

wherein each said different address sub-group includes first and second address locations to which said control logic circuitry writes each succeeding translated protocol byte having a common subject content, from a common signal source, in alternating fashion to an available one of said first and second address locations; and

wherein the host computer retrieves said translated protocol signal bytes from said first and second address locations in alternating fashion, and provides a signal manifestation to said control logic circuitry indicative of the available one of said first and second address locations as that location from which a data bytes has been most recently retrieved by the host computer.

5. The apparatus of claim 4, wherein said control logic circuitry signal writes said succeeding translated protocol bytes for storage at said first and second address locations, and the host computer retrieves the stored translated protocol bytes from said first and second address locations, in an ordered, cyclic fashion, in dependence on said signal manifestation.

6. The apparatus of claim 5, wherein said signal manifestation is a bistable signal, the alternating states of which correspond to an assigned one of said first and second address locations, the presence of each said assigned state being indicative of the availability of its associated address location for signal storage of a translated protocol byte by said control logic circuitry.

7. The apparatus of claim 1, wherein said control logic circuitry further includes CSDB protocol error circuitry responsive to each said accepted frame for determining the presence of the known number of data bytes in each message block, and for preventing said translation of a message block having an incorrect number of data bytes.

8. The apparatus of claim 7, wherein said CSD protocol error circuitry is further responsive to the parity bit in each data byte, for preventing said translation of a data byte having an incorrect parity.

9. The apparatus of claim 1, wherein said serial receiver of said CSDB interface circuitry provides buffered storage of each received CSDB frame pending the acceptance and, alternately, the rejection of the received frame by said control logic circuitry.

10. The apparatus of claim 9, wherein said serial receiver is a Universal Asynchronous Receiver Transmitter (UART).

11. The method of translating the signal protocol of serial bit message blocks presented from identified signal sources over a Commercial Standard Digital Bus (CSDB) to a host computer in each of a plurality of succeeding frames, each frame including a synchronization message block followed by one or more data message blocks, each data message block having an address byte which identifies its subject content, and a known number of data bytes, each data byte having a plurality of data bits and a parity bit, the method comprising:

receiving the CSDB frames and providing a synch enable signal in response to the presence of a synchronization message in each received frame;

accepting and rejecting each received frame in the presence and absence, respectively, of said synch enable signal;

identifying the signal characteristics of each accepted frame message from its address byte;

translating the CSDB signal protocol of each identified subject data byte to the signal protocol of the host computer;

providing plural groups of address locations in signal memory, each said address group being accessible to the host computer; and

storing said translated protocol data byte to address locations in assigned one of said groups of address locations in dependence on the signal characteristics of said translated protocol data bytes.

12. The method of claim 11:

wherein the step of providing includes;

identifying each accepted frame as being associated with an identified signal source, and

designating different ones of said address groups as being associated with different ones of the signal sources; and

wherein the step of storing includes;

writing the translated protocol data bytes from an identified common signal source to an address location in the associated one of said address groups.

13. The method of claim 12 wherein the step of designating includes:

dividing each said address group, as a parent group, into one or more sub-groups of addressable locations; and

assigning each said address sub-group to receive, for storage therein, translated protocol data bytes having a common subject content and received from the signal source associated with said parent group.

14. The method of claim 13, wherein said step of assigning further includes:

establishing first and second address locations in each said different address sub-group to which said control logic circuitry writes each succeeding translated protocol byte having a common subject content, from a common signal source, in alternating fashion to an available one of said first and second address locations, whereby the host computer retrieves each stored translated protocol signal byte from said first and second address locations in alternating fashion, and provides a signal manifestation of the available one of said first and second address locations as that location from which a data bytes has been most recently retrieved by the host computer.

15. The method of claim 14, wherein said step of storing includes:

writing said succeeding translated protocol bytes for storage at said first and second address locations in an ordered, cyclic fashion, in dependence on said signal manifestation.

16. The method of claim 15, wherein said signal manifestation in said step of establishing, is a bistable signal, the alternating states of which correspond to an assigned one of said first and second address locations, the presence of a given one of the bistable signal states being indicative of the availability of its associated address location for signal storage of a translated protocol byte.

17. The method of claim 11, further including:

determining the presence of the known number of data bytes in each message block, and preventing said translating of a message block having an incorrect number of data bytes.

18. The method of claim 17, further including:

checking the state of the parity bit in each data byte, for preventing said translating of a data byte having an incorrect parity.