Memory tester with data compression
First Claim
1. A memory test system comprising:
- a) a semiconductor memory tester;
b) means, within the semiconductor memory tester, for generating a stream of data representing faulty cells within a memory under test;
c) an output device;
d) a bus connecting the output device to the semiconductor memory tester; and
e) a display processor, connected to receive the stream of data as an input and to provide a processed stream of data as an output on the bus, the display processor comprising a lossless data compression circuit.
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Accused Products
Abstract
A semiconductor memory test system with improved fault data processing and display capabilities. The memory tester includes a lossless data compressor for failure data. Compression allows failure data to be more rapidly transferred to a display device that is part of a work station controlling the memory tester. It also reduces the amount of data that must be stored in the display memory, thereby providing a cost effective way to store data from multiple tests. By allowing data for multiple tests to be stored, the data from a prior test can be used to control the formatting of data for a subsequent test. Such formatting is useful for such things as observing failure mechanisms as the operating temperature or speed of the semiconductor memory under test increases.
34 Citations
20 Claims
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1. A memory test system comprising:
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a) a semiconductor memory tester;
b) means, within the semiconductor memory tester, for generating a stream of data representing faulty cells within a memory under test;
c) an output device;
d) a bus connecting the output device to the semiconductor memory tester; and
e) a display processor, connected to receive the stream of data as an input and to provide a processed stream of data as an output on the bus, the display processor comprising a lossless data compression circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory test system comprising:
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a) a semiconductor memory tester;
b) means, within the semiconductor memory tester, for generating a stream of data representing faulty cells within a memory under test;
c) an output device;
d) a display processor, connected to receive the stream of data as an input and to provide a processed stream of data to the output device, the display processor comprising a gating circuit having a first data input and a second data input, the first data input coupled to the stream of data as an input, the gating circuit comprising means for combining values at the first data input with values at the second data input in accordance with a programmable function to provide the processed data output;
e) at least one memory having an input and an output, the at least one memory connected to selectively receive the processed data at its input and to provide data from its output to the second data input of the gating circuit. - View Dependent Claims (11, 12, 13, 14, 15, 16)
a) means, within the display processor, for compressing the processed data stream;
b) means, connected between the output of the at least one memory and the second data input of the display processor, for decompressing data.
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16. The memory test system of claim 10 additionally comprising:
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a) a counter connected to the output of the gating circuit; and
b) an error stack for receiving the output of the counter after the display processor has processed data for a test.
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17. A memory test system comprising:
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a) a semiconductor memory tester;
b) means, within the semiconductor memory tester, for generating a stream of data representing faulty cells within a memory under test;
c) a display processor, connected to receive the stream of data as an input, including a run length encoder, the run length encoder providing as an output a compressed data stream. - View Dependent Claims (18, 19, 20)
a) a display memory with an input and an output, b) a work station connected to receive data from the display processor, with the run length encoder connected to compress data read at the output of the display memory.
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20. The memory test system of claim 19 additionally comprising:
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a) a work station with a display means; and
b) a bus connecting the work station to the display processor with the run length encoder directly connected to the display memory.
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Specification