Storage unit, method of checking storage unit, reading and writing method

• US 6,360,346 B1
• Filed: 08/26/1998
• Issued: 03/19/2002
• Est. Priority Date: 08/27/1997
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Hattori, Masayuki, Miyauchi, Toshiyuki
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US09/140,005
• Time in Patent Office: 1,301 Days
• Field of Search: 714/763, 714/773
• US Class Current: 714/763
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check

Abstract

A storage unit is provided which is capable of preventing the occurrence of readout errors even if two or more errors arise within a code, and a storage unit checking method is offered which can improve the productivity. Write data produced by BCH-encoding and compacting data s1 inputted into a flash memory, capable of correcting two errors within a code in an encoder, is written in a cell array. Data read out from the cell array 3 is error-corrected and decoded in an error correction/encoder to generate output data. In the check to be made at manufacturing (or putting on the market), examination data written in advance is successively read out by one block so that the errors within each code is counted. If the number of errors assumes 1 or less, that code is subjected to error correction, whereas the block including a code whose error number is 2 or more is treated as a defective block. The acceptance or failure is determined depending upon, for example, whether the rate of the number of defective blocks to the total number of blocks is below or not less than 1%.

Claims

1. A storage unit having flash memory and integrated error correction placed within one package, comprising:

an encoding section for encoding data in 512 bit units with an error correcting code of 20 bits for correcting up to 2 errors within each 512 bit unit;

a storage section for storing data encoded by said encoding section;

an error correcting section for correcting errors in the encoded data read out from said storage section;

comprising;

a syndrome generator for generating a syndrome signal calculated on the basis of the encoded data read out from said storage section;

a polynomial deriving circuit for deriving an error position polynomial based on said syndrome signal;

an error position detecting circuit for detecting an error position based on said error position polynomial and outputting an error position signal indicating the position of errors within each 512 bit unit;

a counter for counting the number of errors indicated by said error position signal;

a delay circuit for delaying a copy of the encoded data read out from said storage section; and

an adder for adding said error position signal to the delayed encoded data thereby correcting errors in the data; and

a decoding section for decoding the data corrected by said error correction section.

2. A storage unit as defined in claim 1, further comprising a correction non-operating signal for disabling the correction of data by said error correcting section.

3. A storage unit as defined in claim 1, wherein said storage section is composed of a plurality of storage elements.

4. A storage unit as defined in claim 1, wherein said error correcting code is a shortened BCH code.

5. A method of error correction for a storage unit having flash memory and integrated error correction placed in one package, said method comprising the steps of:

encoding data in 512 bit units with an error correcting code of 20 bits for correcting up to 2 errors within each 512 bit unit;

storing data encoded in said encoding step in a storage section;

correcting errors in the encoded data read out from said storage section by;

generating a syndrome signal calculated on the basis of the encoded data read out from said storage section;

deriving an error position polynomial based on said syndrome signal;

detecting an error position based on said error position polynomial and outputting an error position signal indicating the position of errors within each 512 bit unit;

counting the number of errors indicated by said error position signal;

delaying a copy of the encoded data read out from said storage section; and

adding said error position signal to the delayed encoded data thereby correcting errors in the data; and

decoding the data corrected in said error correcting step.

6. A method as defined in claim 5, further comprising a control step of controlling the correction of data on the basis of an external control signal.

7. A storage unit having flash memory and integrated error correction placed within one package, comprising:

an encoding section for encoding data in 128 byte units with an error correcting code of 4 bytes for correcting up to 2 errors within each 128 byte unit;

a storage section for storing data encoded by said encoding section;

an error correcting section for correcting errors in the encoded data read out from said storage section;

comprising;

a syndrome generator for generating a syndrome signal calculated on the basis of the encoded data read out from said storage section;

a polynomial deriving circuit for deriving an error position polynomial based on said syndrome signal;

an error position detecting circuit for detecting an error position based on said error position polynomial and outputting an error position signal indicating the position of errors within each 128 byte unit;

a counter for counting the number of errors indicated by said error position signal;

a delay circuit for delaying a copy of the encoded data read out from said storage section; and

an adder for adding said error position signal to the delayed encoded data thereby correcting errors in the data; and

a decoding section for decoding the data corrected by said error correction section.

8. A storage unit as defined in claim 7, wherein said error correcting code is a shortened Reed-Solomon code.

9. A method of error correction for a storage unit having flash memory and integrated error correction placed in one package, said method comprising the steps of:

encoding data in 128 byte units with an error correcting code of 4 bytes for correcting up to 2 errors within each 128 byte unit;

storing data encoded in said encoding step in a storage section;

correcting errors in the encoded data read out from said storage section by;

generating a syndrome signal calculated on the basis of the encoded data read out from said storage section;

deriving an error position polynomial based on said syndrome signal;

detecting an error position based on said error position polynomial and outputting an error position signal indicating the position of errors within each 128 byte unit;

counting the number of errors indicated by said error position signal;

delaying a copy of the encoded data read out from said storage section; and

adding said error position signal to the delayed encoded data thereby correcting errors in the data; and

decoding the data corrected in said error correcting step.