Method and system for performing circuit analysis on an integrated-circuit design having design data available in different forms

• US 6,360,350 B1
• Filed: 10/07/1997
• Issued: 03/19/2002
• Est. Priority Date: 10/07/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Corporation (Kleangas Energy Technologies, Inc.)
• Inventors: Gabele, Carol Ivash, Watson, Jean-Paul, Quay, Stephen Thomas, Villarrubia, Paul Gerard, Patel, Parsotam Trikam
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US08/944,975
• Time in Patent Office: 1,624 Days
• Field of Search: 395/500.02, 395/500.03, 395/500.06, 395/500.07, 716/1, 716/2, 716/5, 716/6
• US Class Current: 716/113
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A method for performing circuit analysis on an integrated-circuit design having design data available in different forms is disclosed. In accordance with the method and system of the present invention, the integrated-circuit design includes multiple networks, and the different forms of design data may appear within one of the networks. For all of the networks within the integrated-circuit design, different forms of design data are categorized into at least three databases. The first of the at least three databases may contain three-dimensional extraction information, the second of the databases may contain wiring information, and the third of the databases may contain pre-wiring information. For each of the networks, a determination is made as to whether or not three-dimensional extraction information is available. In response to a determination that three-dimensional extraction information is available, performing circuit analysis by utilizing the three-dimensional extraction information.

Claims

1. A method for performing circuit analysis on an integrated circuit design having a plurality of networks, wherein each of said plurality of networks includes design data available in a format according to a design stage, said method comprising the steps of:

categorizing design data within said integrated circuit design into one of at least three categories according to said design data'"'"'s format, wherein a first of said at least three categories contains only logical circuit information, a second of said at least three categories contains wiring information, and a third of said at least three categories contains three-dimensional extraction information;

performing a first circuit analysis on a network within said integrated circuit to design, in response to a determination that only logical circuit information is available within said network, utilizing said only logical circuit information within said first of said at least three categories;

performing a second circuit analysis on a network within said integrated circuit design, in response to a determination that wiring information is available within said network, utilizing said wiring information within said second of said at least three categories; and

performing a third circuit analysis on a network within said integrated circuit design, in response to a determination that three-dimensional extraction information is available within said network, utilizing said three-dimensional extraction information within said third of said at least three categories, such that circuit analysis can be performed on said integrated circuit design at any given design stage;

and wherein said first circuit analysis step further includes a step of estimating a wire route utilizing said logical design information, a step of calculating wire capacitance by utilizing s aid estimated wire route, and a step of estimating total parasitic capacitance of said network by utilizing said calculated wire capacitance.

2. The method according to claim 1, wherein said third circuit analysis step further includes a step of calculating total parasitic capacitance of said network utilizing said three-dimensional extraction information.

3. The method according to claim 1, wherein said second circuit analysis step further includes a step of calculating wire capacitance by utilizing said wiring information and a step of estimating total parasitic capacitance of said network by utilizing said calculated wire capacitance.

4. The method according to claim 1, wherein said three categories are three databases.

5. A computer system for performing circuit analysis on an integrated circuit design having a plurality of networks, wherein each of said plurality of networks includes design data available in a format according to a design stage, said computer system comprising:

means for categorizing design data within said integrated circuit design into one of at least three categories according to said design data'"'"'s format, wherein a first of said at least three categories contains only logical circuit information, a second of said at least three categories contains wiring information, and a third of said at least three categories contains three-dimensional extraction information;

means for performing a first circuit analysis on a network within said integrated circuit design, in response to a determination that only logical circuit information is available within said network, utilizing said only logical circuit information within said first of said at least three categories;

means for performing a second circuit analysis on a network within said integrated circuit design, in response to a determination that wiring information is available within said network, utilizing said Wiring information within said second of said at least three categories; and

means for performing a third circuit analysis on a network within said integrated circuit design, in response to a determination that three-dimensional extraction information is available within said network, utilizing said three-dimensional extraction information within said third of said at least three categories, such that circuit analysis can be performed on said integrated circuit design at any given design stage;

and wherein said means for performing first circuit analysis step further includes a means for estimating a wire route utilizing said logical design information, a means for calculating wire capacitance utilizing said estimated wire route, and a means for estimating total parasitic capacitance of said network by utilizing said calculated wire capacitance.

6. The computer system according to claim 5, wherein said means for performing a third circuit analysis further includes a means for calculating total parasitic capacitance of said network utilizing said three-dimensional extraction information.

7. The computer system according claim 5, wherein said means for performing a second circuit analysis further includes a means for calculating wire capacitance utilizing said wiring information and a means for estimating total parasitic capacitance of said network by utilizing said calculated wire capacitance.

8. The computer system according to claim 5, wherein said three categories are three databases.

9. A computer program product residing on a computer usable medium for performing circuit analysis on an integrated circuit design having a plurality of networks, wherein each of said plurality of networks includes design data available in a format according to a design stage, said computer program product comprising:

program code means for categorizing design data within said integrated circuit design into one of at least three categories according to said design data'"'"'s format, wherein a first of said at least three categories contains only logical circuit information, a second of said at least three categories contains wiring information, and a third of said at least three categories contains three-dimensional extraction information;

program code means for performing a first circuit analysis on a network within said integrated circuit design, in response to a determination that only logical circuit information is available within said network, utilizing said only logical circuit information within said first of said at least three categories;

program code means for performing a second circuit analysis on a network within said integrated circuit design, in response to a determination that wiring information is available within said network, utilizing said wiring information within said second of said at least three categories; and

program code means for performing a third circuit analysis on a network within said integrated circuit design, in response to a determination that three-dimensional extraction information is available within said network, utilizing said three-dimensional extraction information within said third of said at least three categories, such that circuit analysis can be performed on said integrated circuit design at any given design stage;

and wherein said program code means for performing first circuit analysis step further includes a program code means for estimating a wire route utilizing said logical design information, a program code means for calculating wire capacitance utilizing said estimated wire route, and a program code means for estimating total parasitic capacitance of said network by utilizing said calculated wire capacitance.

10. The computer program product according to claim 9, wherein said program code means for performing a third circuit analysis further includes a program code means for calculating total parasitic capacitance of said network utilizing said three-dimensional extraction information.

11. The computer program product according to claim 9, wherein said program code means for performing a second circuit analysis further includes a program code means for calculating wire capacitance utilizing said wiring information and a program code means for estimating total parasitic capacitance of said network by utilizing said calculated wire capacitance.

12. The computer program product according to claim 9, wherein said three categories are three databases.