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Digital circuit layout techniques

  • US 6,360,352 B2
  • Filed: 07/17/1998
  • Issued: 03/19/2002
  • Est. Priority Date: 07/17/1998
  • Status: Expired due to Term
First Claim
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1. A method comprising:

  • decomposing an input circuit having logic gates into one or more fanout-free regions;

    generating one or more quasi-canonical models for logic gates of the one or more fanout-free regions;

    generating a swap structure from the one or more quasi-canonical models to identify symmetric structures;

    analyzing the swap structure to identify pin swap groups of input pins; and

    swapping one or more input pins to create an equivalent input circuit.

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