Method for coupling to semiconductor device in an integrated circuit having edge-defined, sub-lithographic conductors

• US 6,362,043 B2
• Filed: 02/08/2001
• Issued: 03/26/2002
• Est. Priority Date: 04/25/1997
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Noble, Wendell P.
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US09/779,090
• Publication Number:
  US 20010008784A1
• Time in Patent Office: 411 Days
• Field of Search: 438/241, 438/253, 438/396, 438/672, 438/675, 438/947, 438/239, 438/381, 257/301, 257/306, 257/303, 257/905
• US Class Current: 438/253
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/312 with a bit line higher than the capacitor
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 12/488 Word lines
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench
• CPC Class Codes: Y10S 438/947 Subphotolithographic processing

Abstract

An integrated circuit comprising stacked capacitor memory cells having sub-lithographic, edge-defined word lines and a method for forming such an integrated circuit. The method forms conductors adjacent to sub-lithographic word lines in order to couple a stacked capacitor to the access transistor of the memory cell. The conductors are bounded by the word lines. The bit line and capacitor are formed with a single mask image in such a manner as to self-align the bit line and the capacitor and to maximize the capacitance of the memory device. The method may be used to couple any suitable circuit element to a semiconductor device in an integrated circuit having edge-defined, sub-lithographic word lines.

Claims

1. A method for forming an integrated circuit using a lithographic process having a minimum lithographic dimension, comprising:

forming a semiconductor device in a semiconductor substrate;

forming a first conductor outwardly from the semiconductor device, the first conductor having a width less than the minimum lithographic dimension;

forming a second conductor outwardly from the semiconductor device, the second conductor being bounded by the first conductor; and

coupling a circuit component to the semiconductor device by the second conductor.

2. The method for forming an integrated circuit according to claim 1, wherein coupling the circuit component to the semiconductor device comprises coupling a storage capacitor to the semiconductor device.

3. The method for forming an integrated circuit according to claim 2, wherein forming a first conductor comprises forming a word line for activating the transistor.

4. The method for forming an integrated circuit according to claim 1, wherein forming a semiconductor device comprises forming a transistor for accessing the storage capacitor.

5. The method for forming an integrated circuit according to claim 4, wherein forming a first conductor comprises forming a word line for activating the transistor.

6. The method for forming an integrated circuit according to claim 1, wherein forming the second conductor includes self-aligning the second conductor with the circuit component using a single mask image.

7. A method of forming an integrated circuit using a lithographic process having a minimum lithographic dimension, comprising:

forming a semiconductor device in a semiconductor substrate;

forming a mandrel over the semiconductor device and a portion of the semiconductor substrate;

removing a portion of the mandrel over part of the semiconductor device to create a groove in the mandrel and to expose sidewalls in the mandrel;

filling the groove with a conductive material; and

etching the conductive material leaving conductive sidewalls having a sub-lithographic dimension and being adjacent the sidewalls in the mandrel.

8. The method of claim 7, wherein etching the conductive material includes anisotropically etching the conductive material intermediate the sidewalls in the mandrel.

9. The method of claim 7, wherein removing the portion of the mandrel includes etching the portion of the mandrel.

10. The method of claim 7, wherein forming the mandrel includes depositing an intrinsic poly-silicon on the semiconductor device and the portion of the semiconductor substrate.

11. The method of claim 7, wherein filling the groove includes filing the groove with a polysilicon conductive material.

12. The method of claim 7, wherein removing the portion of the mandrel includes, after etching the conductive material, removing the remainder of the mandrel.

13. The method of claim 7, wherein the steps are performed in the listed order.

14. A method of forming an integrated circuit using a lithographic process having a minimum lithographic dimension, comprising:

forming a semiconductor device in a semiconductor substrate;

forming a mandrel over the semiconductor device and a portion of the semiconductor substrate;

removing a portion of the mandrel over part of the semiconductor device to create a groove in the mandrel and to expose sidewalls in the mandrel, one of the side walls being aligned with the semiconductor device;

filling the groove with a conductive material; and

etching the conductive material leaving conductive sidewalls having a sub-lithographic dimension and being adjacent the sidewalls in the mandrel, one of the conductive sidewalls being connected to and aligned with the semiconductor device.

15. The method of claim 14, wherein etching the conductive material includes anisotropically etching the conductive material intermediate the sidewalls in the mandrel.

16. The method of claim 14, wherein removing the portion of the mandrel includes etching the portion of the mandrel.

17. The method of claim 14, wherein forming the mandrel includes depositing an intrinsic polysilicon on the semiconductor device and the portion of the semiconductor substrate.

18. The method of claim 14, wherein filling the groove includes filing the groove with a polysilicon conductive material.

19. The method of claim 14, wherein removing the portion of the mandrel includes, after etching the conductive material, removing the remainder of the mandrel.

20. The method of claim 14, wherein the steps are performed in the listed order.

21. A method of forming wordlines in a memory array using a lithographic process having a minimum lithographic dimension, comprising:

forming a transistor on a semiconductor substrate;

forming a mandrel over the transistor;

removing a portion of the mandrel over the transistor to create a groove in the mandrel and to expose sidewalls in the mandrel, one of the side walls being aligned with a gate of the transistor;

filling the groove with a conductive material; and

etching the conductive material leaving conductive sidewalls having a sub-lithographic dimension and being adjacent the sidewalls in the mandrel, one of the conductive sidewalls being connected to and aligned with the semiconductor device.

22. A method of forming a memory device a lithographic process having a minimum lithographic dimension, comprising:

forming a plurality of transistors in a semiconductor substrate, a pair of the transistors having a shared drain, each of the transistors having a gate and a source, the gate of each transistor extending outwardly from the semiconductor substrate;

forming a plurality of word lines outwardly from the transistors, each word line having a width less than the minimum lithographic dimension;

connecting the plurality of word lines to the gates of the transistors for activating the transistors;

forming a bit line and a plurality of conductors outwardly from the transistors adjacent the word lines;

connecting the bit line to the shared drain of the pair of transistors;

connecting each conductor to the source of a different transistor; and

forming a plurality of storage capacitors outwardly from the bit line and the conductors, each storage capacitor coupled a source of a different transistor by a different conductor.

23. The method according to claim 22, wherein forming the plurality of word lines includes forming a first word line connected to and extending outwardly from a first one of the pair of transistors and forming a second word line connected to and extending outwardly from a second one of the pair of transistors.

24. The method according to claim 23, wherein forming the bit line includes forming the bit line intermediate the first word line and the second word line.

25. The method according to claim 23, wherein forming the plurality of word lines includes forming a third of word line outside the first word line and forming a fourth of word line outside the second word line.

26. The method according to claim 25, wherein forming the third word line includes passing the third word line past the pair of transistors such that the third word line is free of electrical connection to the pair of transistors.

27. The method according to claim 26, wherein forming the fourth word line includes passing the fourth word line past the pair of transistors such that the fourth word line is free of electrical connection to the pair of transistors.

28. The method according to claim 25, wherein forming the plurality of conductors includes forming a first conductor between the first word line and the third word line and forming a second conductor between the second word line and the fourth word line.

29. A method of forming a memory device with a lithographic process having a minimum lithographic dimension, comprising:

forming a plurality of transistors in a semiconductor substrate, a pair of the transistors having a shared drain, each of the transistors having a gate and a source, the gate of each transistor extending outwardly from the semiconductor substrate;

forming a first word line outwardly from the gate of a first of the pair of the transistors, the first word line having a width less than the minimum lithographic dimension;

forming a second word line outwardly from the gate of a second of the pair of the transistors, the second word line having a width less than the minimum lithographic dimension;

forming a third word line outwardly from the gate of a third transistor, the third word line having a width less than the minimum lithographic dimension, wherein the third word line bounds the first word line;

forming a fourth word line outwardly from the gate of a fourth transistor, the fourth word line having a width less than the minimum lithographic dimension, wherein the fourth word line bounds the second word line;

forming a bit line between the first word line and the second word line and in connection with the shared drain of the pair of transistors;

forming a first conductor intermediate the first word line and the third word line and outwardly from the source of the first transistor;

forming a second conductor intermediate the second word line and the fourth word line and outwardly from the source of the second transistor; and

forming a plurality of storage capacitors outwardly from the word lines and the conductors, a first of the storage capacitors being coupled the source of the first transistor through the first conductor, a second of the storage capacitors being coupled the source of the second transistor through the second conductor.

30. An integrated circuit formed using a lithographic process having a minimum lithographic dimension, comprising:

a semiconductor device formed in a semiconductor substrate;

an edge-defined, first conductor formed outwardly from the semiconductor device, the first conductor having a width less than the minimum lithographic dimension;

a second conductor formed outwardly from the semiconductor device, the second conductor bounding the first conductor; and

a circuit element coupled to the semiconductor device by the second conductor.

31. The circuit according to claim 30, wherein the circuit element is a storage capacitor.

32. The circuit according to claim 31, wherein the semiconductor device is a transistor for accessing the storage capacitor.

33. The circuit according to claim 32, wherein the first conductor is a word line for activating the transistor.

34. The circuit according to claim 33, wherein the first conductor is a poly-silicon material.

35. The circuit according to claim 32, wherein the second conductor couples a source of the transistor to a bottom storage plate of the storage capacitor.

36. The circuit according to claim 30, wherein the second conductor includes an insulating sleeve separating the second conductor from the first conductor.

37. The circuit according to claim 30, wherein the first conductor includes an insulator layer extending outwardly from the semiconductor device and separating the first conductor from the second conductor.

38. The circuit according to claim 30, wherein the first conductor includes an insulative cap, the insulative cap separating the first conductor from the circuit element.

39. An integrated circuit formed using a lithographic process having a minimum lithographic dimension, comprising:

a transistor formed in a semiconductor substrate;

an edge-defined word line formed outwardly from the transistor, the word line having a width less than the minimum lithographic dimension and being adapted to activate the transistor;

a second conductor formed outwardly from the transistor, the second conductor bounding the word line;

a storage capacitor coupled to the transistor by the second conductor; and

a bit line formed outwardly from the transistor.

40. The integrated circuit according to claim 39, wherein the bit line is bounded by the word line.

41. The integrated circuit device according to claim 39, wherein the bit line and the storage capacitor are formed using a single mask image.

42. An integrated circuit formed using a lithographic process having a minimum lithographic dimension, comprising:

a semiconductor device formed in a semiconductor substrate;

a first conductor formed outwardly from the semiconductor device, the first conductor having a width less than the minimum lithographic dimension;

a second conductor formed outwardly from the semiconductor device, the second conductor adjacent to the first conductor; and

a circuit element formed above the first conductor and the second conductor and coupled to the semiconductor device by the second conductor.

43. The integrated circuit according to claim 42, further comprising a bit line formed outwardly from the semiconductor device and wherein the circuit element is a storage capacitor, the semiconductor device is a transistor for coupling the bit line to the storage capacitor through the second conductor, and the first conductor is a word line for activating the transistor.

44. The integrated circuit according to claim 43, wherein the word line is bounded by the second conductor and the bit line.

45. The integrated circuit device according to claim 43, wherein the bit line and the storage capacitor are formed using a single mask image.

46. The integrated circuit device according to claim 43, wherein the first conductor is edge-defined.

47. An integrated circuit memory device formed using a lithographic process having a minimum lithographic dimension, comprising:

a transistor formed in a semiconductor substrate;

a word line formed outwardly from the transistor, the word line having a width less than the minimum lithographic dimension;

a second conductor formed outwardly from the transistor, the second conductor being adjacent to the word line;

a bit line formed outwardly from the transistor; and

a storage capacitor formed above the word line and the second conductor and coupled to the transistor by the second conductor.

48. The memory device according to claim 47, wherein the word line is edge-defined.

49. The memory device according to claim 47, wherein the bit line includes a first region adjacent the word line and a second region adjacent the storage capacitor.

50. The memory device according to claim 49, wherein the bit line includes a third region adjacent a gate of the transistor.

51. The memory device according to claim 50, wherein the gate of the transistor is aligned with the word line.

52. The memory device according to claim 49, wherein the bit line includes a third region outwardly of the storage capacitor.

53. An integrated circuit memory device formed from a process having a minimum lithographic dimension, comprising:

a substrate;

an active region in the substrate;

a wiring region outwardly of the active region, the wiring region including word lines having a dimension less than the minimum lithographic dimension; and

a stacked capacitor region outwardly of the wiring region, wherein the wiring region does not spatially limit storage capacitor size in the stacked capacitor region.

54. The memory device according to claim 53, wherein the wiring region includes all of the word lines, and wherein the word lines are connected to semi-conductor elements in the active region.

55. The memory device according to claim 53, wherein the word lines activate semi-conductor elements in the active region, and wherein the stacked capacitor region is free of word lines.

56. The memory device according to claim 53, wherein the active region includes a transistor, a first of the word lines being outwardly of and connected to the transistor for activating same, wherein the wiring region includes a first conductor formed adjacent the first word line, and wherein the stacked capacitor region includes a stacked capacitor connected to the transistor through the first conductor.

57. The memory device according to claim 56, wherein the wiring region includes a bit line formed outwardly from and connected to the transistor.